Closed-loop 1×N VLSI design system

• Main Authors: RASHID IRFAN, CORREALE, JR. ANTHONY, BAKER MATTHEW W, STEINMETZ PAUL M, BOWERS BENJAMIN J
• Format: Patent
• Language: English
• Published: 06.03.2012
• Subjects: CALCULATING; COMPUTING; COUNTING; ELECTRIC DIGITAL DATA PROCESSING; PHYSICS

Embodiments that design integrated circuits using a closed loop 1×N methodology are disclosed. Some embodiments create a physical design representation based on a behavioral representation of a design for an integrated circuit. The behavioral representation may comprise RTL HDL with one or more 1×N building blocks. The embodiments may alter elements of the 1×N building block by using logic design tools, synthesis tools, physical design tools, and timing analysis tools. Further embodiments comprise an apparatus having a viewer and a 1×N compiler. The viewer may generate displays of behavioral representations of 1×N building blocks, with the behavioral representations comprising RTL definitions. The 1×N compiler may create physical design representations of the 1×N building block and create behavioral representations from the physical design representations, wherein the physical design representations have elements altered by one or more tools of a tool suite.