Methods and apparatuses to support memory transactions using partial physical addresses
Methods and apparatuses to support memory transactions using partial physical addresses are disclosed. Method embodiments generally comprise home agents monitoring multiple responses to multiple memory requests, wherein at least one of the responses has a partial address for a memory line, resolving...
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Main Authors | , |
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Format | Patent |
Language | English |
Published |
06.03.2012
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Subjects | |
Online Access | Get full text |
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