High performance chip carrier substrate

A multilayer chip carrier with increased space for power distribution PTHs and reduced power-related noise. In a multilayer chip carrier with two signal redistribution fanout layers, in addition to signal escape from near-edge signal pads at the first fanout layer, remaining signal pads are moved cl...

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Bibliographic Details
Main Authors AUDET JEAN, MEMIS IRVING
Format Patent
LanguageEnglish
Published 04.01.2011
Subjects
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