Forming interconnects with air gaps
Disclosed is a process of an integration method to form an air gap in an interconnect. On top of a metal wiring layer on a semiconductor substrate is deposited a dielectric cap layer followed by a sacrificial dielectric layer and pattern transfer layers. A pattern is transferred through the pattern...
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Main Authors | , , , , , , |
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Format | Patent |
Language | English |
Published |
07.09.2010
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Subjects | |
Online Access | Get full text |
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Abstract | Disclosed is a process of an integration method to form an air gap in an interconnect. On top of a metal wiring layer on a semiconductor substrate is deposited a dielectric cap layer followed by a sacrificial dielectric layer and pattern transfer layers. A pattern is transferred through the pattern transfer layers, sacrificial dielectric layer, dielectric cap layer and into the metal wiring layer. The presence of the sacrificial dielectric layer aids in controlling the thickness and profile of the dielectric cap layer which in turn affects reliability of the interconnect. |
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AbstractList | Disclosed is a process of an integration method to form an air gap in an interconnect. On top of a metal wiring layer on a semiconductor substrate is deposited a dielectric cap layer followed by a sacrificial dielectric layer and pattern transfer layers. A pattern is transferred through the pattern transfer layers, sacrificial dielectric layer, dielectric cap layer and into the metal wiring layer. The presence of the sacrificial dielectric layer aids in controlling the thickness and profile of the dielectric cap layer which in turn affects reliability of the interconnect. |
Author | CLEVENGER LAWRENCE A CHOI SAMUEL S. S PONOTH SHOM EDELSTEIN DANIEL C LEUNG PAK DARNON MAXIME NITTA SATYANARAYANA VENKATA |
Author_xml | – fullname: CHOI SAMUEL S. S – fullname: NITTA SATYANARAYANA VENKATA – fullname: LEUNG PAK – fullname: DARNON MAXIME – fullname: PONOTH SHOM – fullname: CLEVENGER LAWRENCE A – fullname: EDELSTEIN DANIEL C |
BookMark | eNrjYmDJy89L5WRQdssvys3MS1fIzCtJLUrOz8tLTS4pVijPLMlQSMwsUkhPLCjmYWBNS8wpTuWF0twMCm6uIc4euqkF-fGpxQWJyal5qSXxocHm5pYGZgaGTobGRCgBAIc_KAg |
ContentType | Patent |
DBID | EVB |
DatabaseName | esp@cenet |
DatabaseTitleList | |
Database_xml | – sequence: 1 dbid: EVB name: esp@cenet url: http://worldwide.espacenet.com/singleLineSearch?locale=en_EP sourceTypes: Open Access Repository |
DeliveryMethod | fulltext_linktorsrc |
Discipline | Medicine Chemistry Sciences |
ExternalDocumentID | US7790601B1 |
GroupedDBID | EVB |
ID | FETCH-epo_espacenet_US7790601B13 |
IEDL.DBID | EVB |
IngestDate | Fri Jul 19 12:35:02 EDT 2024 |
IsOpenAccess | true |
IsPeerReviewed | false |
IsScholarly | false |
Language | English |
LinkModel | DirectLink |
MergedId | FETCHMERGED-epo_espacenet_US7790601B13 |
Notes | Application Number: US20090561651 |
OpenAccessLink | https://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20100907&DB=EPODOC&CC=US&NR=7790601B1 |
ParticipantIDs | epo_espacenet_US7790601B1 |
PublicationCentury | 2000 |
PublicationDate | 20100907 |
PublicationDateYYYYMMDD | 2010-09-07 |
PublicationDate_xml | – month: 09 year: 2010 text: 20100907 day: 07 |
PublicationDecade | 2010 |
PublicationYear | 2010 |
RelatedCompanies | INTERNATIONAL BUSINESS MACHINES CORPORATION FREESCALE SEMICONDUCTOR INC |
RelatedCompanies_xml | – name: INTERNATIONAL BUSINESS MACHINES CORPORATION – name: FREESCALE SEMICONDUCTOR INC |
Score | 2.7876933 |
Snippet | Disclosed is a process of an integration method to form an air gap in an interconnect. On top of a metal wiring layer on a semiconductor substrate is deposited... |
SourceID | epo |
SourceType | Open Access Repository |
SubjectTerms | BASIC ELECTRIC ELEMENTS ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY SEMICONDUCTOR DEVICES |
Title | Forming interconnects with air gaps |
URI | https://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20100907&DB=EPODOC&locale=&CC=US&NR=7790601B1 |
hasFullText | 1 |
inHoldings | 1 |
isFullTextHit | |
isPrint | |
link | http://utb.summon.serialssolutions.com/2.0.0/link/0/eLvHCXMwfV1LS8NAEB5KFfWmVbG-WFByCyZmk3YPQciLIvSBbaS3ktlsSi5tSCL-fXdjWr3obdmF2QfMe-ZbgEfbtpiUjIbOuWHrlDuZniA6epKiRZmwTMxUaGA8cUYxfV3ayw7ku16YBif0swFHlBzFJb_XjbwufoJYQVNbWT1hLqe2L9HCDbTWOzalxWAMtMBzw9k0mPqa77vxXJu8uQpWT_oennSUDpQVrWD2w3dPNaUUvzVKdAqHM0lsU59BR2x6cOzvPl7rwdG4zXfLYct61Tk8RFtVtrImCuCh5Ko-hdcVUXFUkuQlWSdFdQEkChf-SJe7rfY3W8Xz_bmsS-hKh19cATGEM0wRn9FAShlNWMY4YpayIUvRFFYf-n-Suf5n7QZOvnPfqm3pFrp1-SHupEqt8b55jC8R4nu7 |
link.rule.ids | 230,309,786,891,25594,76904 |
linkProvider | European Patent Office |
linkToHtml | http://utb.summon.serialssolutions.com/2.0.0/link/0/eLvHCXMwfV1LS8NAEB5KFetNq2J9BpTcgol5tHsIQpKGqH1hW-ktZDab0ktbkoh_39nYVi96W3Zh9gEzs9_szLcA97ZtMrKMusa5bmsWdzItQXS0JEXTYsI0MJOhgf7AiabWy8ye1WCxrYWpeEI_K3JE0ihO-l5W9nr9E8QKqtzK4gEX1LV6CiduoG7QsUE3Br2tBp7bHQ2Doa_6vjsdq4M3V9LqEfbwCCjttQkRSpr97rsni1LWvz1KeAT7IxK2LI-hJpZNaPjbj9eacNDfvHdTc6N6xQnchSuZtjJXJMFDzmV-Ci8LRcZRlWSRK_NkXZyCEnYnfqTRbPFuZ_F0vFuXeQZ1AvziHBRdOJ0U8RF1tCxmJSxjHDFLWYelaAizBa0_xVz8M3YLjWjS78W958HrJRx-v4PLEqYrqJf5h7gm91riTXUwXwDYfqY |
openUrl | ctx_ver=Z39.88-2004&ctx_enc=info%3Aofi%2Fenc%3AUTF-8&rfr_id=info%3Asid%2Fsummon.serialssolutions.com&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Apatent&rft.title=Forming+interconnects+with+air+gaps&rft.inventor=CHOI+SAMUEL+S.+S&rft.inventor=NITTA+SATYANARAYANA+VENKATA&rft.inventor=LEUNG+PAK&rft.inventor=DARNON+MAXIME&rft.inventor=PONOTH+SHOM&rft.inventor=CLEVENGER+LAWRENCE+A&rft.inventor=EDELSTEIN+DANIEL+C&rft.date=2010-09-07&rft.externalDBID=B1&rft.externalDocID=US7790601B1 |