Decoding control with address transition detection in page erase function

Circuits and methods are provided for controlling multi-page erase operations in flash memory. The page address of each address of a multi-page erase operation is latched in wordline decoders. A page select reset generator circuit processes the block addresses of each address of the multi-page erase...

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Bibliographic Details
Main Author PYEON HONG BEOM
Format Patent
LanguageEnglish
Published 17.08.2010
Subjects
INFORMATION STORAGE
PHYSICS
STATIC STORES
Online AccessGet full text

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