Ultra scalable high speed heterojunction vertical n-channel MISFETs and methods thereof

A method for forming and the structure of a strained vertical channel of a field effect transistor, a field effect transistor and CMOS circuitry is described incorporating a drain, body and source region on a sidewall of a vertical single crystal semiconductor structure wherein a hetero-junction is...

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Bibliographic Details
Main Authors CHU JACK OON, OUYANG QIQING CHRISTINE
Format Patent
LanguageEnglish
Published 16.03.2010
Subjects
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