Semiconductor memory device and semiconductor integrated circuit system

In a semiconductor memory device including resistance change memory devices, when a resistance change memory device is in standby mode, the two terminals of the resistance change memory device, i.e., a bit line and a source line, are set at a precharge potential Vp, respectively. At the time of a se...

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Bibliographic Details
Main Authors YAMAMOTO YASUE, KIKUKAWA HIROHITO, SHIRAHAMA MASANORI, AGATA YASUHIRO
Format Patent
LanguageEnglish
Published 14.04.2009
Subjects
INFORMATION STORAGE
PHYSICS
STATIC STORES
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Summary:In a semiconductor memory device including resistance change memory devices, when a resistance change memory device is in standby mode, the two terminals of the resistance change memory device, i.e., a bit line and a source line, are set at a precharge potential Vp, respectively. At the time of a set operation, the bit line is set to a set voltage Vd, which is higher than the precharge potential Vp, while the source line is grounded. At the time of a reset operation, bit line is grounded, while the source line is set to the set voltage Vd. At the time of a data-read operation, the source line is grounded by a read bias generation circuit, while the potential of the bit line is kept at the precharge potential Vp.
Bibliography:Application Number: US20070712480