Contact resistance and capacitance for semiconductor devices
A method generates a design layout for an integrated circuit. A design is provided for an integrated circuit. Library cells are selected according to the design. The library cells are mapped into a chip area map. Unmapped cells are filled with filler cells. Critical cells of the library cells are se...
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Main Authors | , , |
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Format | Patent |
Language | English |
Published |
21.10.2008
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Subjects | |
Online Access | Get full text |
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