Contact resistance and capacitance for semiconductor devices

A method generates a design layout for an integrated circuit. A design is provided for an integrated circuit. Library cells are selected according to the design. The library cells are mapped into a chip area map. Unmapped cells are filled with filler cells. Critical cells of the library cells are se...

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Main Authors GURUMURTHY GIRISHANKAR, SHAH DHARIN NAYESHBHAI, SAVITHRI NAGARAJ N
Format Patent
LanguageEnglish
Published 21.10.2008
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Abstract A method generates a design layout for an integrated circuit. A design is provided for an integrated circuit. Library cells are selected according to the design. The library cells are mapped into a chip area map. Unmapped cells are filled with filler cells. Critical cells of the library cells are selected. The selected critical cells are altered with respect to contact resistance and/or contact capacitance. The map including the altered cells is provided as the design layout.
AbstractList A method generates a design layout for an integrated circuit. A design is provided for an integrated circuit. Library cells are selected according to the design. The library cells are mapped into a chip area map. Unmapped cells are filled with filler cells. Critical cells of the library cells are selected. The selected critical cells are altered with respect to contact resistance and/or contact capacitance. The map including the altered cells is provided as the design layout.
Author SAVITHRI NAGARAJ N
GURUMURTHY GIRISHANKAR
SHAH DHARIN NAYESHBHAI
Author_xml – fullname: GURUMURTHY GIRISHANKAR
– fullname: SHAH DHARIN NAYESHBHAI
– fullname: SAVITHRI NAGARAJ N
BookMark eNrjYmDJy89L5WSwcc7PK0lMLlEoSi3OLC5JzEtOVUjMS1FITixITM6E8NPyixSKU3Mzk_PzUkqTS4C8lNSyzOTUYh4G1rTEnOJUXijNzaDg5hri7KGbWpAfn1oMNCE1L7UkPjTY3MTE0MjQwsnImAglAL6bMa4
ContentType Patent
DBID EVB
DatabaseName esp@cenet
DatabaseTitleList
Database_xml – sequence: 1
  dbid: EVB
  name: esp@cenet
  url: http://worldwide.espacenet.com/singleLineSearch?locale=en_EP
  sourceTypes: Open Access Repository
DeliveryMethod fulltext_linktorsrc
Discipline Medicine
Chemistry
Sciences
Physics
ExternalDocumentID US7441218B2
GroupedDBID EVB
ID FETCH-epo_espacenet_US7441218B23
IEDL.DBID EVB
IngestDate Fri Jul 19 12:02:19 EDT 2024
IsOpenAccess true
IsPeerReviewed false
IsScholarly false
Language English
LinkModel DirectLink
MergedId FETCHMERGED-epo_espacenet_US7441218B23
Notes Application Number: US20060440657
OpenAccessLink https://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20081021&DB=EPODOC&CC=US&NR=7441218B2
ParticipantIDs epo_espacenet_US7441218B2
PublicationCentury 2000
PublicationDate 20081021
PublicationDateYYYYMMDD 2008-10-21
PublicationDate_xml – month: 10
  year: 2008
  text: 20081021
  day: 21
PublicationDecade 2000
PublicationYear 2008
RelatedCompanies TEXAS INSTRUMENTS INCORPORATED
RelatedCompanies_xml – name: TEXAS INSTRUMENTS INCORPORATED
Score 2.716725
Snippet A method generates a design layout for an integrated circuit. A design is provided for an integrated circuit. Library cells are selected according to the...
SourceID epo
SourceType Open Access Repository
SubjectTerms CALCULATING
CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION ORPROCESSING OF GOODS
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC
GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS
PHYSICS
TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINSTCLIMATE CHANGE
Title Contact resistance and capacitance for semiconductor devices
URI https://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20081021&DB=EPODOC&locale=&CC=US&NR=7441218B2
hasFullText 1
inHoldings 1
isFullTextHit
isPrint
link http://utb.summon.serialssolutions.com/2.0.0/link/0/eLvHCXMwfV1LS8QwEB6W9XnTquz6ogfprajZdtOCReiLRdgH7lb2tjRpCr20i634953EdvWix0xgmARmvklm8gXgjtqMp5Q4sntKlhm5MJnNHkzi2GKc0pwwVYqZzsaTxHpZ2-seFN1bGMUT-qnIEdGjOPp7o-L19ucSK1S9lfU9K1BUPccrLzS607Ejf6o2Qt-LFvNwHhhB4CVLY_bqUYR9RDMfo_UeZtFUOkP05stHKdvfiBKfwP4ClZXNKfREqcFR0H28psHhtK13a3CgGjR5jcLWCeszeJKMUilvdDwpy-wPpXpaZjpH3OPF9xhTUb2Wfe9VKQldcZQJFRPOQY-jVTAx0aDNbvGbZLkzfXQB_bIqxQB0Tng-EpitUOFaVsZTkrmWa2VOyijJHXcIwz_VXP4zdwXHpCV8JY_X0G_eP8QNom7DbtV-fQHnd4d3
link.rule.ids 230,309,783,888,25576,76876
linkProvider European Patent Office
linkToHtml http://utb.summon.serialssolutions.com/2.0.0/link/0/eLvHCXMwfV1LT8MwDLam8Rg3KKCNZw-otwnI2qWVqJDWdhqwl1iLdquaNJN6aSdaxN_HCd3gAsc4kuVEsj8ndr4A3FCL8YQSW3ZPyTIjF11msbsusS3RT-iKMFWKmUz7o8h8XlrLBmSbtzCKJ_RTkSOiR3H090rF6_XPJZaveivLW5ahqHgchq5vbE7Htvyp2vAHbjCf-TPP8Dw3WhjTV5ci7COaDTBa72CGTaUzBG8D-Shl_RtRhoewO0dleXUEDZFr0PI2H69psD-p690a7KkGTV6isHbC8hgeJKNUwisdT8oy-0OpnuSpzhH3ePY9xlRUL2Xfe5FLQlccpULFhBPQh0HojbpoULxdfBwttqb3TqGZF7log84JX_UEZitUOKaZ8oSkjumYqZ0wSla204HOn2rO_pm7htYonIzj8dP05RwOSE3-Su4voFm9f4hLROCKXam9-wJtyopq
openUrl ctx_ver=Z39.88-2004&ctx_enc=info%3Aofi%2Fenc%3AUTF-8&rfr_id=info%3Asid%2Fsummon.serialssolutions.com&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Apatent&rft.title=Contact+resistance+and+capacitance+for+semiconductor+devices&rft.inventor=GURUMURTHY+GIRISHANKAR&rft.inventor=SHAH+DHARIN+NAYESHBHAI&rft.inventor=SAVITHRI+NAGARAJ+N&rft.date=2008-10-21&rft.externalDBID=B2&rft.externalDocID=US7441218B2