Reduced glitch dynamic logic circuit and method of synthesis for complementary oxide semiconductor (CMOS) and strained/unstrained silicon-on-insulator (SOI)
The present invention implements structures and method for non-delayed clock dynamic logic circuit configurations with output and/or complementary output with reduced glitch and/or mitigating adverse charge-sharing effects for Complementary Oxide Semiconductor (CMOS) and/or mitigating parasitic bipo...
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| Main Authors | , |
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| Format | Patent |
| Language | English |
| Published |
30.09.2008
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| Subjects | |
| Online Access | Get full text |
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| Abstract | The present invention implements structures and method for non-delayed clock dynamic logic circuit configurations with output and/or complementary output with reduced glitch and/or mitigating adverse charge-sharing effects for Complementary Oxide Semiconductor (CMOS) and/or mitigating parasitic bipolar action in Strained/Unstrained Silicon-On-Insulator (SOI) circuits, where insulator may be oxide, nitride of Silicon and the like or Sapphire and the like including a method of synthesis. |
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| AbstractList | The present invention implements structures and method for non-delayed clock dynamic logic circuit configurations with output and/or complementary output with reduced glitch and/or mitigating adverse charge-sharing effects for Complementary Oxide Semiconductor (CMOS) and/or mitigating parasitic bipolar action in Strained/Unstrained Silicon-On-Insulator (SOI) circuits, where insulator may be oxide, nitride of Silicon and the like or Sapphire and the like including a method of synthesis. |
| Author | SINGH NIRMAL RANA AMAR PAL SINGH |
| Author_xml | – fullname: SINGH NIRMAL – fullname: RANA AMAR PAL SINGH |
| BookMark | eNqNjMFqwkAQhnOoh1b7DnPUQ1C00PRaUexBAkbPYdmdJAObmZDZgHkXH7artHdh-Oc_fP_3lrywML4mtxO6waKD2lOwDbiRTUsWvNQxLfV2oACGHbQYGnEgFejIoUElhUp6sNJ2HlvkYPoR5EoOQTE6hKM5RGK-PebF4iHR0BtidMuB_yso-TucxiPWwZvHpsh_FrNkUhmv-P73pwnsd-ftIcVOStTOWGQM5aX4_Fh_Zdnqe715AvkFuoNU7w |
| ContentType | Patent |
| DBID | EVB |
| DatabaseName | esp@cenet |
| DatabaseTitleList | |
| Database_xml | – sequence: 1 dbid: EVB name: esp@cenet url: http://worldwide.espacenet.com/singleLineSearch?locale=en_EP sourceTypes: Open Access Repository |
| DeliveryMethod | fulltext_linktorsrc |
| Discipline | Medicine Chemistry Sciences |
| ExternalDocumentID | US7429880B2 |
| GroupedDBID | EVB |
| ID | FETCH-epo_espacenet_US7429880B23 |
| IEDL.DBID | EVB |
| IngestDate | Fri Jul 19 12:02:15 EDT 2024 |
| IsOpenAccess | true |
| IsPeerReviewed | false |
| IsScholarly | false |
| Language | English |
| LinkModel | DirectLink |
| MergedId | FETCHMERGED-epo_espacenet_US7429880B23 |
| Notes | Application Number: US20030638756 |
| OpenAccessLink | https://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20080930&DB=EPODOC&CC=US&NR=7429880B2 |
| ParticipantIDs | epo_espacenet_US7429880B2 |
| PublicationCentury | 2000 |
| PublicationDate | 20080930 |
| PublicationDateYYYYMMDD | 2008-09-30 |
| PublicationDate_xml | – month: 09 year: 2008 text: 20080930 day: 30 |
| PublicationDecade | 2000 |
| PublicationYear | 2008 |
| Score | 2.7207732 |
| Snippet | The present invention implements structures and method for non-delayed clock dynamic logic circuit configurations with output and/or complementary output with... |
| SourceID | epo |
| SourceType | Open Access Repository |
| SubjectTerms | BASIC ELECTRONIC CIRCUITRY ELECTRICITY PULSE TECHNIQUE |
| Title | Reduced glitch dynamic logic circuit and method of synthesis for complementary oxide semiconductor (CMOS) and strained/unstrained silicon-on-insulator (SOI) |
| URI | https://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20080930&DB=EPODOC&locale=&CC=US&NR=7429880B2 |
| hasFullText | 1 |
| inHoldings | 1 |
| isFullTextHit | |
| isPrint | |
| link | http://utb.summon.serialssolutions.com/2.0.0/link/0/eLvHCXMwfV1bS8MwFA5jivqmU3HeOA9S3EPZLdXuoQhrN6awdayb7G20TasFScfSofsv_lhPsnXzRaEPoU0DSXtuyXfOR8idwR7rMYsNHfVjrFMWh7pJTZkFgvY8COMmq8kE5_7goTehL1NjWiBJnguj6oR-quKIKFEhynum9PV8t4nlKGylqAYJ3kqfumPL0fLo2MQAvaY5baszdB3X1mzbmnjaYGRhBNjCX7WN2npPetGyzH7ntS2TUua_LUr3mOwPcTCenZBCxEvk0M6J10rkoL8578bmRvTEKfkeySKrEYM3dJzDd2BrKnlQugvCZBEukwx8zmBNCg1pDGLF0b8TiQB0TUGhx9dg8cUK0i-cPgiJjU-5LPqKPe7tvutV1CBCcUdErLrkeRNE8iE763gpCLuv3vHc58oZgW5nbPd0nOZsu6SzibddkOY5KfKURxcEFGsNNQKzTg3KfCa3hRrUDCRDetNvtMqk_Ocwl_88uyJHO5jFNSlmi2V0g7Y8C27VV_gBlrWm8w |
| link.rule.ids | 230,309,786,891,25594,76904 |
| linkProvider | European Patent Office |
| linkToHtml | http://utb.summon.serialssolutions.com/2.0.0/link/0/eLvHCXMwfV1bT8IwFG6IGvFNUSNe-2AWeVi4dTIeFhM2CChjhIHhjWzrpktMR-iI8l_8sZ4WBr5osodm65q027m13zkfQvcabVQjGmkq6MdIJTQKVJ3oIgsE7LkfRHVaEQnO9uCxOyHPU22aQ3GWCyPrhH7K4oggUQHIeyr19Xy3iWVJbCUv-zHcSp46Y8NSsuhYhwC9olgtoz10LMdUTNOYuMpgZEAE2IRftQXaer8BEaEos99-bYmklPlvi9I5RgdDGIylJygXsgLKmxnxWgEd2pvzbmhuRI-fou-RKLIaUvwGjnPwjumaSh5L3YWDeBEs4xR7jOI1KTROIsxXDPw7HnMMrimW6PE1WHyxwskXTB9zgY1PmCj6Cj0eTNtxS3IQLrkjQlpesqyJefwhOqtwSQi7J99xnV7pDOFOe2x2VZjmbLuks4m7XZD6OdpjCQsvEJasNUTz9SrRCPWo2BaqEd0XDOl1r9YsouKfw1z-8-wO5btjuz_r9wYvV-hoB7m4RnvpYhnegF1P_Vv5RX4AjL6p3g |
| openUrl | ctx_ver=Z39.88-2004&ctx_enc=info%3Aofi%2Fenc%3AUTF-8&rfr_id=info%3Asid%2Fsummon.serialssolutions.com&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Apatent&rft.title=Reduced+glitch+dynamic+logic+circuit+and+method+of+synthesis+for+complementary+oxide+semiconductor+%28CMOS%29+and+strained%2Funstrained+silicon-on-insulator+%28SOI%29&rft.inventor=SINGH+NIRMAL&rft.inventor=RANA+AMAR+PAL+SINGH&rft.date=2008-09-30&rft.externalDBID=B2&rft.externalDocID=US7429880B2 |