Method of making stacked die package
A method of making a stacked die package ( 39 ) includes placing a first flip chip die ( 16 ) on a base carrier ( 12 ) and electrically connecting the first flip chip die ( 16 ) to the base carrier ( 12 ). A second flip chip die ( 18 ) is attached back-to-back to the first flip chip die ( 16 ) and e...
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Main Author | |
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Format | Patent |
Language | English |
Published |
27.05.2008
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Subjects | |
Online Access | Get full text |
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Abstract | A method of making a stacked die package ( 39 ) includes placing a first flip chip die ( 16 ) on a base carrier ( 12 ) and electrically connecting the first flip chip die ( 16 ) to the base carrier ( 12 ). A second flip chip die ( 18 ) is attached back-to-back to the first flip chip die ( 16 ) and electrically connected to the base carrier ( 12 ) with a plurality of insulated wires ( 20 ). A mold compound ( 36 ) is formed over the first and second dice and one surface of the base carrier. |
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AbstractList | A method of making a stacked die package ( 39 ) includes placing a first flip chip die ( 16 ) on a base carrier ( 12 ) and electrically connecting the first flip chip die ( 16 ) to the base carrier ( 12 ). A second flip chip die ( 18 ) is attached back-to-back to the first flip chip die ( 16 ) and electrically connected to the base carrier ( 12 ) with a plurality of insulated wires ( 20 ). A mold compound ( 36 ) is formed over the first and second dice and one surface of the base carrier. |
Author | LO WAI YEW |
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Notes | Application Number: US20060524457 |
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RelatedCompanies | FREESCALE SEMICONDUCTOR, INC |
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Snippet | A method of making a stacked die package ( 39 ) includes placing a first flip chip die ( 16 ) on a base carrier ( 12 ) and electrically connecting the first... |
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SubjectTerms | BASIC ELECTRIC ELEMENTS ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY SEMICONDUCTOR DEVICES |
Title | Method of making stacked die package |
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