Memory address generating circuit and memory controller using the same

• Main Author: LIM MIN-SOO
• Format: Patent
• Language: English
• Published: 05.02.2008
• Subjects: INFORMATION STORAGE; PHYSICS; STATIC STORES

Provided are a memory address generating circuit through which a user can freely select a method of generating an address of a memory according to an environment in which the memory is applied, and a memory controller including the memory address generating circuit. The memory address generating circuit includes a CAS address selecting circuit and an RAS address selecting circuit. The CAS address selecting circuit outputs a CAS address signal using N (N is an integer) column address signals and M (M is an integer) CAS address select signals. The RAS address selecting circuit which outputs an RAS address signal using K (K is an integer) row address signals and L (L is an integer) RAS address select signals. The memory address generating circuit controls the CAS address select signals and the RAS address select signals to perform a memory mapping most suitable for a system in which the memory is used.