Etch selectivity inversion for etching along crystallographic directions in silicon

Methods for expanding trenches are disclosed. A trench is formed in a substrate having side walls including at least two crystallographic planes. One crystallographic plane is etchable at a faster rate than a second crystallographic plane. A dielectric layer is selectively grown on surfaces of the c...

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Bibliographic Details
Main Author KUDELKA STEPHAN
Format Patent
LanguageEnglish
Published 20.05.2003
Edition7
Subjects
BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
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Summary:Methods for expanding trenches are disclosed. A trench is formed in a substrate having side walls including at least two crystallographic planes. One crystallographic plane is etchable at a faster rate than a second crystallographic plane. A dielectric layer is selectively grown on surfaces of the crystallographic planes such that the dielectric layer includes a greater thickness on one of the crystallographic plane than on the other. The dielectric layer and the substrate are etched such that an etch rate inversion is achieved. That is, the second crystallographic plane is effectively etched at a faster rate than the first crystallographic plane.
Bibliography:Application Number: US20010893157