Semiconductor integrated circuit and method of checking memory

A test circuit comprised of a microprogram controlled control unit for generating a test pattern (addresses and data) for each memory in accordance with a predetermined algorithm and reading written data, an arithmetic unit, and data determining means for determinating the read data and outputting t...

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Main Authors SHIMIZU ISAO, SATOU MASAYUKI, FUKIAGE HIROSHI
Format Patent
LanguageEnglish
Published 15.10.2002
Edition7
Subjects
INFORMATION STORAGE
PHYSICS
STATIC STORES
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Abstract A test circuit comprised of a microprogram controlled control unit for generating a test pattern (addresses and data) for each memory in accordance with a predetermined algorithm and reading written data, an arithmetic unit, and data determining means for determinating the read data and outputting the result of determination is provided over a semiconductor chip equipped with a memory.
AbstractList A test circuit comprised of a microprogram controlled control unit for generating a test pattern (addresses and data) for each memory in accordance with a predetermined algorithm and reading written data, an arithmetic unit, and data determining means for determinating the read data and outputting the result of determination is provided over a semiconductor chip equipped with a memory.
Author SHIMIZU ISAO
FUKIAGE HIROSHI
SATOU MASAYUKI
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Snippet A test circuit comprised of a microprogram controlled control unit for generating a test pattern (addresses and data) for each memory in accordance with a...
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SubjectTerms INFORMATION STORAGE
PHYSICS
STATIC STORES
Title Semiconductor integrated circuit and method of checking memory
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