Method of manufacturing DRAM capacitor
A method of manufacturing DRAM capacitor. An active region is formed above a substrate. A plurality of parallel word lines is formed above the substrate. A first plug and a second plug are formed between the word lines in locations for forming the desired bit line contact and node contact, respectiv...
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Main Authors | , , , , , , , |
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Format | Patent |
Language | English |
Published |
05.03.2002
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Edition | 7 |
Subjects | |
Online Access | Get full text |
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Abstract | A method of manufacturing DRAM capacitor. An active region is formed above a substrate. A plurality of parallel word lines is formed above the substrate. A first plug and a second plug are formed between the word lines in locations for forming the desired bit line contact and node contact, respectively. Insulation material is deposited into the remaining space between the word lines. A bit line contact is formed above the first plug. A plurality of parallel bit lines is formed above the substrate. The bit lines are perpendicular to the word lines. The bit line is electrically connected to the substrate through the bit line contact and the first plug. The bit lines are electrically insulated from each other. Furthermore, each bit line is covered on top by a hard material layer. Finally, a node contact is formed over the second plug. |
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AbstractList | A method of manufacturing DRAM capacitor. An active region is formed above a substrate. A plurality of parallel word lines is formed above the substrate. A first plug and a second plug are formed between the word lines in locations for forming the desired bit line contact and node contact, respectively. Insulation material is deposited into the remaining space between the word lines. A bit line contact is formed above the first plug. A plurality of parallel bit lines is formed above the substrate. The bit lines are perpendicular to the word lines. The bit line is electrically connected to the substrate through the bit line contact and the first plug. The bit lines are electrically insulated from each other. Furthermore, each bit line is covered on top by a hard material layer. Finally, a node contact is formed over the second plug. |
Author | WANG LI-MING HUANG SEN-HUAN HSIEH WEN-KUEI TSAI HONG-HSIANG LIU HAOCHIEH SHEU BOR-RU CHANG JUNG-HO CHEN HSIUAN |
Author_xml | – fullname: LIU HAOCHIEH – fullname: WANG LI-MING – fullname: HSIEH WEN-KUEI – fullname: CHEN HSIUAN – fullname: CHANG JUNG-HO – fullname: TSAI HONG-HSIANG – fullname: SHEU BOR-RU – fullname: HUANG SEN-HUAN |
BookMark | eNrjYmDJy89L5WRQ800tychPUchPU8hNzCtNS0wuKS3KzEtXcAly9FVITixITM4syS_iYWBNS8wpTuWF0twMCm6uIc4euqkF-fGpxUBVqXmpJfGhwWbGpkYWlmZOhsZEKAEA27worQ |
ContentType | Patent |
DBID | EVB |
DatabaseName | esp@cenet |
DatabaseTitleList | |
Database_xml | – sequence: 1 dbid: EVB name: esp@cenet url: http://worldwide.espacenet.com/singleLineSearch?locale=en_EP sourceTypes: Open Access Repository |
DeliveryMethod | fulltext_linktorsrc |
Discipline | Medicine Chemistry Sciences |
Edition | 7 |
ExternalDocumentID | US6352896B1 |
GroupedDBID | EVB |
ID | FETCH-epo_espacenet_US6352896B13 |
IEDL.DBID | EVB |
IngestDate | Fri Aug 16 05:58:26 EDT 2024 |
IsOpenAccess | true |
IsPeerReviewed | false |
IsScholarly | false |
Language | English |
LinkModel | DirectLink |
MergedId | FETCHMERGED-epo_espacenet_US6352896B13 |
Notes | Application Number: US20000618597 |
OpenAccessLink | https://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20020305&DB=EPODOC&CC=US&NR=6352896B1 |
ParticipantIDs | epo_espacenet_US6352896B1 |
PublicationCentury | 2000 |
PublicationDate | 20020305 |
PublicationDateYYYYMMDD | 2002-03-05 |
PublicationDate_xml | – month: 03 year: 2002 text: 20020305 day: 05 |
PublicationDecade | 2000 |
PublicationYear | 2002 |
RelatedCompanies | WINBOND ELECTRONICS CORP |
RelatedCompanies_xml | – name: WINBOND ELECTRONICS CORP |
Score | 2.5522296 |
Snippet | A method of manufacturing DRAM capacitor. An active region is formed above a substrate. A plurality of parallel word lines is formed above the substrate. A... |
SourceID | epo |
SourceType | Open Access Repository |
SubjectTerms | ELECTRICITY |
Title | Method of manufacturing DRAM capacitor |
URI | https://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20020305&DB=EPODOC&locale=&CC=US&NR=6352896B1 |
hasFullText | 1 |
inHoldings | 1 |
isFullTextHit | |
isPrint | |
link | http://utb.summon.serialssolutions.com/2.0.0/link/0/eLvHCXMwfV3NS8MwFH-MKbqbTsXND3KQ3oq0STt7KGK_GEK3sa2y20hKAjvYja3Df9-XsE4vegsJvHyQl19e8n7vATy5JR1ow8LG2wS1mfJ8O6CM2UpjA3WlDBzNd85H_rBg7wtv0YJVw4UxcUK_THBE1KgS9b025_Xm5xErMb6Vu2exwqr1azYPE6uxjl29f60kCtPJOBnHVhyHxcwaTUNfRzEJ_AgNpRO8Rb9o77_0I9KklM1vRMku4HSCwqr6Elqy6sJ53CRe68JZfvjvxuJB9XZXYOUm1zNZK_LJq70mJBiGIUmmbzkpEfNKVM7tNZAsncdDGztcHie3LGbHodEbaKPNL2-BOKUKHI8j9nLFhJBcMB2VRlFEZC646kHvTzH9f9ruoGPSmWgnKu8e2vV2Lx8QVWvxaNbjGzASeuM |
link.rule.ids | 230,309,786,891,25585,76894 |
linkProvider | European Patent Office |
linkToHtml | http://utb.summon.serialssolutions.com/2.0.0/link/0/eLvHCXMwfV3PS8MwFH6MKc6bTsX5MwfprUibttJDEduuVF27sbWyW0lKAzvYja3Df9-XsE4vegsJ5Bd5-fKSfN8DeDBL-iQdCx1PE1S3hO3oLrUsXUhsoGZVuYbkOyepE-fW29yed2DRcmGUTuiXEkdEiyrR3hu1X69-LrFC9bdy88gXmLV8jjIv1Frv2JTrVwt9bzgZh-NACwIvn2np1HOkionr-OgoHeAJ25Uy-8MPX5JSVr8RJTqBwwlWVjen0KnqPvSCNvBaH46S3Xs3JnemtzkDLVGxnslSkE9WbyUhQTEMSTh9SUiJmFeica7PgUTDLIh1bLDYD67IZ_uu0Qvoos9fXQIxSuEaNkPsZcLivGLckqo0giIiM87EAAZ_VnP1T9k99OIsGRWj1_T9Go5VaBP5ocq-gW6z3la3iLANv1Nz8w0eX33W |
openUrl | ctx_ver=Z39.88-2004&ctx_enc=info%3Aofi%2Fenc%3AUTF-8&rfr_id=info%3Asid%2Fsummon.serialssolutions.com&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Apatent&rft.title=Method+of+manufacturing+DRAM+capacitor&rft.inventor=LIU+HAOCHIEH&rft.inventor=WANG+LI-MING&rft.inventor=HSIEH+WEN-KUEI&rft.inventor=CHEN+HSIUAN&rft.inventor=CHANG+JUNG-HO&rft.inventor=TSAI+HONG-HSIANG&rft.inventor=SHEU+BOR-RU&rft.inventor=HUANG+SEN-HUAN&rft.date=2002-03-05&rft.externalDBID=B1&rft.externalDocID=US6352896B1 |