Semiconductor chip package

• Main Authors: NEVILL LELAND R, KING JERROLD L
• Format: Patent
• Language: English
• Published: 06.03.2001
• Edition: 7
• Subjects: CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION ORPROCESSING OF GOODS; ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR; ELECTRICITY; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS; MEASURING; MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES; PHYSICS; PRINTED CIRCUITS; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS; TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINSTCLIMATE CHANGE; TESTING

An improved semiconductor chip package capable of independently aligning with testing equipment during the manufacturing phase of electrical testing. Independent alignment is realized by directly connecting the semiconductor chip package to the test alignment apparatus by fitting together two substantially conforming surfaces, one on the chip package and one on the alignment apparatus. The conforming surfaces are arranged so that only one matable position is achievable. The substantially conforming surfaces equate to three substantially conical indentations on the chip package and three substantially conical protrusions or protuberances of substantially conforming size and depth extending from the alignment apparatus. Once fitted, the three protrusions suspend the semiconductor chip in a substantially horizontal plane so that electrical test contacts, also substantially in a horizontal plane, may be easily contacted with the conductive leads extending generally horizontally and co-planar from the semiconductor chip.