Lading plug contact pattern for DRAM application
A method of fabricating a semiconductor device having a landing plug is provided. First, a substrate is provided, which has active areas, wordlines stretching over the active areas and an isolation layer filling the gaps between the wordlines. Second, a pattern is defined and the isolation layer mas...
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Main Authors | , |
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Format | Patent |
Language | English |
Published |
13.02.2001
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Edition | 7 |
Subjects | |
Online Access | Get full text |
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Abstract | A method of fabricating a semiconductor device having a landing plug is provided. First, a substrate is provided, which has active areas, wordlines stretching over the active areas and an isolation layer filling the gaps between the wordlines. Second, a pattern is defined and the isolation layer masked with the pattern is etched for the formation of bitline and node contacts, wherein the pattern has a protrusion which shortens the length of the bitline to wordline overlap formed thereby. Finally, the contacts are filled with a conducting layer. |
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AbstractList | A method of fabricating a semiconductor device having a landing plug is provided. First, a substrate is provided, which has active areas, wordlines stretching over the active areas and an isolation layer filling the gaps between the wordlines. Second, a pattern is defined and the isolation layer masked with the pattern is etched for the formation of bitline and node contacts, wherein the pattern has a protrusion which shortens the length of the bitline to wordline overlap formed thereby. Finally, the contacts are filled with a conducting layer. |
Author | HUANG SEN-HUAN CHEN HSIUAN |
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RelatedCompanies | WINBOND ELECTRONICS CORPORATION |
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Snippet | A method of fabricating a semiconductor device having a landing plug is provided. First, a substrate is provided, which has active areas, wordlines stretching... |
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SubjectTerms | ELECTRICITY |
Title | Lading plug contact pattern for DRAM application |
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