Lading plug contact pattern for DRAM application
A method of fabricating a semiconductor device having a landing plug is provided. First, a substrate is provided, which has active areas, wordlines stretching over the active areas and an isolation layer filling the gaps between the wordlines. Second, a pattern is defined and the isolation layer mas...
Saved in:
Main Authors | , |
---|---|
Format | Patent |
Language | English |
Published |
13.02.2001
|
Edition | 7 |
Subjects | |
Online Access | Get full text |
Cover
Loading…
Summary: | A method of fabricating a semiconductor device having a landing plug is provided. First, a substrate is provided, which has active areas, wordlines stretching over the active areas and an isolation layer filling the gaps between the wordlines. Second, a pattern is defined and the isolation layer masked with the pattern is etched for the formation of bitline and node contacts, wherein the pattern has a protrusion which shortens the length of the bitline to wordline overlap formed thereby. Finally, the contacts are filled with a conducting layer. |
---|---|
Bibliography: | Application Number: US20000618612 |