Lading plug contact pattern for DRAM application

A method of fabricating a semiconductor device having a landing plug is provided. First, a substrate is provided, which has active areas, wordlines stretching over the active areas and an isolation layer filling the gaps between the wordlines. Second, a pattern is defined and the isolation layer mas...

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Bibliographic Details
Main Authors CHEN HSIUAN, HUANG SEN-HUAN
Format Patent
LanguageEnglish
Published 13.02.2001
Edition7
Subjects
ELECTRICITY
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Summary:A method of fabricating a semiconductor device having a landing plug is provided. First, a substrate is provided, which has active areas, wordlines stretching over the active areas and an isolation layer filling the gaps between the wordlines. Second, a pattern is defined and the isolation layer masked with the pattern is etched for the formation of bitline and node contacts, wherein the pattern has a protrusion which shortens the length of the bitline to wordline overlap formed thereby. Finally, the contacts are filled with a conducting layer.
Bibliography:Application Number: US20000618612