Digital delay-locked loop
The present invention is directed to a digital delay-locked loop for digitally controlling a clock signal delay time and saving synchronization information in a register. After intercepting an input clock signal, the digital delay-locked loop utilizes the saved synchronization information in returni...
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Main Author | |
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Format | Patent |
Language | English |
Published |
21.11.2000
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Edition | 7 |
Subjects | |
Online Access | Get full text |
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Abstract | The present invention is directed to a digital delay-locked loop for digitally controlling a clock signal delay time and saving synchronization information in a register. After intercepting an input clock signal, the digital delay-locked loop utilizes the saved synchronization information in returning to the normal operation, and furthermore, detects a shifted delay by using a trigger pulse generator in order to reduce power consumption during the rapid synchronization of an internal clock signal to an external clock signal, saves a delay state corresponding to a maximum value of half the period of the external clock signal to a lock target rising edge of the internal clock signal, and thus synchronization time and operating time of the digital delay-loop are reduced, which results in reduced operation power for the predetermined time. In addition, even when the external clock signal is suspended, a lock point can be rapidly found and thereby mis-operation because internal clock signals in a circuit are not synchronized to the external clock signal can be minimized. |
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AbstractList | The present invention is directed to a digital delay-locked loop for digitally controlling a clock signal delay time and saving synchronization information in a register. After intercepting an input clock signal, the digital delay-locked loop utilizes the saved synchronization information in returning to the normal operation, and furthermore, detects a shifted delay by using a trigger pulse generator in order to reduce power consumption during the rapid synchronization of an internal clock signal to an external clock signal, saves a delay state corresponding to a maximum value of half the period of the external clock signal to a lock target rising edge of the internal clock signal, and thus synchronization time and operating time of the digital delay-loop are reduced, which results in reduced operation power for the predetermined time. In addition, even when the external clock signal is suspended, a lock point can be rapidly found and thereby mis-operation because internal clock signals in a circuit are not synchronized to the external clock signal can be minimized. |
Author | PARK; BOO-YONG |
Author_xml | – fullname: PARK; BOO-YONG |
BookMark | eNrjYmDJy89L5WSQdMlMzyxJzFFISc1JrNTNyU_OTk1RyMnPL-BhYE1LzClO5YXS3Azybq4hzh66qQX58anFBYnJqXmpJfGhwWaGpgYWppaOxoRVAABSYiOS |
ContentType | Patent |
DBID | EVB |
DatabaseName | esp@cenet |
DatabaseTitleList | |
Database_xml | – sequence: 1 dbid: EVB name: esp@cenet url: http://worldwide.espacenet.com/singleLineSearch?locale=en_EP sourceTypes: Open Access Repository |
DeliveryMethod | fulltext_linktorsrc |
Discipline | Medicine Chemistry Sciences |
Edition | 7 |
ExternalDocumentID | US6150859A |
GroupedDBID | EVB |
ID | FETCH-epo_espacenet_US6150859A3 |
IEDL.DBID | EVB |
IngestDate | Fri Jul 19 11:50:48 EDT 2024 |
IsOpenAccess | true |
IsPeerReviewed | false |
IsScholarly | false |
Language | English |
LinkModel | DirectLink |
MergedId | FETCHMERGED-epo_espacenet_US6150859A3 |
Notes | Application Number: US19980201716 |
OpenAccessLink | https://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20001121&DB=EPODOC&CC=US&NR=6150859A |
ParticipantIDs | epo_espacenet_US6150859A |
PublicationCentury | 2000 |
PublicationDate | 20001121 |
PublicationDateYYYYMMDD | 2000-11-21 |
PublicationDate_xml | – month: 11 year: 2000 text: 20001121 day: 21 |
PublicationDecade | 2000 |
PublicationYear | 2000 |
RelatedCompanies | HYUNDAI ELECTRONICS INDUSTRIES CO., LTD |
RelatedCompanies_xml | – name: HYUNDAI ELECTRONICS INDUSTRIES CO., LTD |
Score | 2.52923 |
Snippet | The present invention is directed to a digital delay-locked loop for digitally controlling a clock signal delay time and saving synchronization information in... |
SourceID | epo |
SourceType | Open Access Repository |
SubjectTerms | AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATIONOF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES BASIC ELECTRONIC CIRCUITRY ELECTRIC COMMUNICATION TECHNIQUE ELECTRICITY PULSE TECHNIQUE TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHICCOMMUNICATION |
Title | Digital delay-locked loop |
URI | https://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20001121&DB=EPODOC&locale=&CC=US&NR=6150859A |
hasFullText | 1 |
inHoldings | 1 |
isFullTextHit | |
isPrint | |
link | http://utb.summon.serialssolutions.com/2.0.0/link/0/eLvHCXMwY2BQSUw1sUwyTkvVTUo1SdE1STJM1bVIMTbRBYomJyammAP7b6BxSF8_M49QE68I0wgmhgzYXhjwOaHl4MMRgTkqGZjfS8DldQFiEMsFvLayWD8pEyiUb-8WYuuiBusdA1OrkaGai5Ota4C_i7-zmrOzbWiwml-QLfjcc1NLR2YGVlAjGnTKvmuYE2hPSgFyheImyMAWADQrr0SIgSk1T5iB0xl275owA4cvdLobyITmvGIRBkmXzHTQ_R4KoFMdK3WBVVB2aopCTn5-gSiDvJtriLOHLtCOeLh34kODYY4xFmNgAXbyUyUYFJKSDRITDZPMgLVvskmSiTmw25JqZJCcmARsYQDbNCaSDBK4TJHCLSXNwAXeOm5oqGtkKMPAUlJUmioLrERLkuTA_gcA3ap2ww |
link.rule.ids | 230,309,786,891,25594,76903 |
linkProvider | European Patent Office |
linkToHtml | http://utb.summon.serialssolutions.com/2.0.0/link/0/eLvHCXMwY2BQSUw1sUwyTkvVTUo1SdE1STJM1bVIMTbRBYomJyammAP7b6BxSF8_M49QE68I0wgmhgzYXhjwOaHl4MMRgTkqGZjfS8DldQFiEMsFvLayWD8pEyiUb-8WYuuiBusdA1OrkaGai5Ota4C_i7-zmrOzbWiwml-QLfjcc1NLR2YGVnNghxDcUQpzAu1JKUCuUNwEGdgCgGbllQgxMKXmCTNwOsPuXRNm4PCFTncDmdCcVyzCIOmSmQ6630MBdKpjpS6wCspOTVHIyc8vEGWQd3MNcfbQBdoRD_dOfGgwzDHGYgwswE5-qgSDQlKyQWKiYZIZsPZNNkkyMQd2W1KNDJITk4AtDGCbxkSSQQKXKVK4peQZOD1CfH3ifTz9vKUZuMDbyA0NdY0MZRhYSopKU2WBFWpJkhw4LACQcHmt |
openUrl | ctx_ver=Z39.88-2004&ctx_enc=info%3Aofi%2Fenc%3AUTF-8&rfr_id=info%3Asid%2Fsummon.serialssolutions.com&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Apatent&rft.title=Digital+delay-locked+loop&rft.inventor=PARK%3B+BOO-YONG&rft.date=2000-11-21&rft.externalDBID=A&rft.externalDocID=US6150859A |