Digital delay-locked loop

• Main Author: PARK; BOO-YONG
• Format: Patent
• Language: English
• Published: 21.11.2000
• Edition: 7
• Subjects: AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATIONOF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES; BASIC ELECTRONIC CIRCUITRY; ELECTRIC COMMUNICATION TECHNIQUE; ELECTRICITY; PULSE TECHNIQUE; TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHICCOMMUNICATION

The present invention is directed to a digital delay-locked loop for digitally controlling a clock signal delay time and saving synchronization information in a register. After intercepting an input clock signal, the digital delay-locked loop utilizes the saved synchronization information in returning to the normal operation, and furthermore, detects a shifted delay by using a trigger pulse generator in order to reduce power consumption during the rapid synchronization of an internal clock signal to an external clock signal, saves a delay state corresponding to a maximum value of half the period of the external clock signal to a lock target rising edge of the internal clock signal, and thus synchronization time and operating time of the digital delay-loop are reduced, which results in reduced operation power for the predetermined time. In addition, even when the external clock signal is suspended, a lock point can be rapidly found and thereby mis-operation because internal clock signals in a circuit are not synchronized to the external clock signal can be minimized.