Synchronous semiconductor memory device having wave pipelining control structure and method for outputting data using the same

A synchronous semiconductor memory device having a wave pipelining control structure and a method of outputting data therefrom. A register for storing the data output from a memory cell is controlled by a control signal in response to first and second external clock signals. The level transition of...

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Bibliographic Details
Main Authors KIM; NAM-JONG, LEE; KYUAN
Format Patent
LanguageEnglish
Published 21.12.1999
Edition6
Subjects
INFORMATION STORAGE
PHYSICS
STATIC STORES
Online AccessGet full text

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