Synchronous semiconductor memory device having wave pipelining control structure and method for outputting data using the same
A synchronous semiconductor memory device having a wave pipelining control structure and a method of outputting data therefrom. A register for storing the data output from a memory cell is controlled by a control signal in response to first and second external clock signals. The level transition of...
Saved in:
Main Authors | , |
---|---|
Format | Patent |
Language | English |
Published |
21.12.1999
|
Edition | 6 |
Subjects | |
Online Access | Get full text |
Cover
Loading…
Be the first to leave a comment!