Circuitry and method for latching information

An output signal is output to a selected one of first and second output nodes in response to an event in which a control node transitions from a first logic state to a second logic state. The selected one of the first and second output nodes is selected in response to a logic state of an input node...

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Main Authors MUHICH; JOHN STEPHEN, NGUYEN; QUAN
Format Patent
LanguageEnglish
Published 14.12.1999
Edition6
Subjects
BASIC ELECTRONIC CIRCUITRY
ELECTRICITY
PULSE TECHNIQUE
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Abstract An output signal is output to a selected one of first and second output nodes in response to an event in which a control node transitions from a first logic state to a second logic state. The selected one of the first and second output nodes is selected in response to a logic state of an input node during the event. A minimum setup time for the logic state of the input node to be stable before the control node transitions to the second logic state is shorter than a minimum time for inverting the logic state of the input node.
AbstractList An output signal is output to a selected one of first and second output nodes in response to an event in which a control node transitions from a first logic state to a second logic state. The selected one of the first and second output nodes is selected in response to a logic state of an input node during the event. A minimum setup time for the logic state of the input node to be stable before the control node transitions to the second logic state is shorter than a minimum time for inverting the logic state of the input node.
Author NGUYEN; QUAN
MUHICH; JOHN STEPHEN
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Snippet An output signal is output to a selected one of first and second output nodes in response to an event in which a control node transitions from a first logic...
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SubjectTerms BASIC ELECTRONIC CIRCUITRY
ELECTRICITY
PULSE TECHNIQUE
Title Circuitry and method for latching information
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