Sense amplifier for use in an EEPROM

A sense amplifier for signal detection for use in an electrically erasable and programmable read-only memory (EEPROM). The sense amplifier includes a first clock signal-synchronized inverter including a first inverter and first switch for switching between activating and deactivating states of the f...

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Main Authors OHUCHI; KAZUNORI, TANAKA; YOSHIYUKI, SUMIHARA; HIDEKI, TANAKA; TOMOHARU, IWATA; YOSHIHISA, MOMODOMI; MASAKI, SAKUI; KOJI, SAITO; SHINJI
Format Patent
LanguageEnglish
Published 14.04.1998
Edition6
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Abstract A sense amplifier for signal detection for use in an electrically erasable and programmable read-only memory (EEPROM). The sense amplifier includes a first clock signal-synchronized inverter including a first inverter and first switch for switching between activating and deactivating states of the first inverter, the first clock signal-synchronized inverter having a first input connected to a corresponding one of the bit lines and a first output. A second clock signal-synchronized inverter is arranged in parallel with the first clock signal-synchronized inverter and includes a second inverter and a second switch for switching between activating and deactivating states of the second inverter, the second clock signal-synchronized inverter having an input connected to the output of the first clock signal-synchronized inverter and an output connected to the input of the first clock signal-synchronized inverter. The switches in the first and second clock signal-synchronized inverters are activated with a delay so that a potential on the corresponding bit line is reliably sensed and latched at the output of the first clock signal-synchronized inverter.
AbstractList A sense amplifier for signal detection for use in an electrically erasable and programmable read-only memory (EEPROM). The sense amplifier includes a first clock signal-synchronized inverter including a first inverter and first switch for switching between activating and deactivating states of the first inverter, the first clock signal-synchronized inverter having a first input connected to a corresponding one of the bit lines and a first output. A second clock signal-synchronized inverter is arranged in parallel with the first clock signal-synchronized inverter and includes a second inverter and a second switch for switching between activating and deactivating states of the second inverter, the second clock signal-synchronized inverter having an input connected to the output of the first clock signal-synchronized inverter and an output connected to the input of the first clock signal-synchronized inverter. The switches in the first and second clock signal-synchronized inverters are activated with a delay so that a potential on the corresponding bit line is reliably sensed and latched at the output of the first clock signal-synchronized inverter.
Author OHUCHI; KAZUNORI
TANAKA; YOSHIYUKI
MOMODOMI; MASAKI
TANAKA; TOMOHARU
SAITO; SHINJI
IWATA; YOSHIHISA
SAKUI; KOJI
SUMIHARA; HIDEKI
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– fullname: TANAKA; TOMOHARU
– fullname: IWATA; YOSHIHISA
– fullname: MOMODOMI; MASAKI
– fullname: SAKUI; KOJI
– fullname: SAITO; SHINJI
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Snippet A sense amplifier for signal detection for use in an electrically erasable and programmable read-only memory (EEPROM). The sense amplifier includes a first...
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SubjectTerms INFORMATION STORAGE
PHYSICS
STATIC STORES
Title Sense amplifier for use in an EEPROM
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