Apparatus for granting either a CPU data bus or a memory data bus or a memory data bus access to a PCI bus

A link system controller is interposed between a PCI bus and the data bus and memory data bus of a personal computer system to normally allow transfer of write information from the PCI bus to DRAM memories on the memory data bus. Whenever a request is made for the transfer of data to the CPU data bu...

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Main Authors WSZOLEK; PHILIP, FALL; BRIAN NEIL, PESAVENTO; RODNEY JAMES, STEELE; JAMES CRAWFORD
Format Patent
LanguageEnglish
Published 24.03.1998
Edition6
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Abstract A link system controller is interposed between a PCI bus and the data bus and memory data bus of a personal computer system to normally allow transfer of write information from the PCI bus to DRAM memories on the memory data bus. Whenever a request is made for the transfer of data to the CPU data bus, a CPU bus interface controller requests release of the system from the DRAM controller. The DRAM controller then grants permission or releases control to the CPU bus interface whenever the DRAM controller is not writing data out to the DRAM data bus. When this release is effected, the transfer of write data to the memory data bus is prevented and transfer of data to the CPU data bus is enabled. This prevents simultaneous switching of the devices on both the CPU data bus and the memory data bus, to reduce the generation of noise; so that the operation of the IC system device is not impaired.
AbstractList A link system controller is interposed between a PCI bus and the data bus and memory data bus of a personal computer system to normally allow transfer of write information from the PCI bus to DRAM memories on the memory data bus. Whenever a request is made for the transfer of data to the CPU data bus, a CPU bus interface controller requests release of the system from the DRAM controller. The DRAM controller then grants permission or releases control to the CPU bus interface whenever the DRAM controller is not writing data out to the DRAM data bus. When this release is effected, the transfer of write data to the memory data bus is prevented and transfer of data to the CPU data bus is enabled. This prevents simultaneous switching of the devices on both the CPU data bus and the memory data bus, to reduce the generation of noise; so that the operation of the IC system device is not impaired.
Author FALL; BRIAN NEIL
PESAVENTO; RODNEY JAMES
STEELE; JAMES CRAWFORD
WSZOLEK; PHILIP
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Snippet A link system controller is interposed between a PCI bus and the data bus and memory data bus of a personal computer system to normally allow transfer of write...
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SubjectTerms CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
Title Apparatus for granting either a CPU data bus or a memory data bus or a memory data bus access to a PCI bus
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