Method and apparatus for controlling timing of execution of saving and restoring operations in a processor system

• Main Authors: MORINAGA; SHIGEKI, KIDA; HIROYUKI, OHBA; MAMORU, WATABE; MITSURU
• Format: Patent
• Language: English
• Published: 24.06.1997
• Edition: 6
• Subjects: CALCULATING; COMPUTING; COUNTING; ELECTRIC DIGITAL DATA PROCESSING; PHYSICS

In a coprocessor system having a central processing unit (CPU), a floating-point processing unit (FPU) and a memory (RAM), coupled with each other through buses, when the CPU issues a save command to the FPU, the FPU discriminates the attribute, i.e., a long command or a short command, of a current...