Memory access device

In a memory access device, each of read and write addresses generated by read and write address generating means is stored in a read or write address buffer through a read or write address latch. The memory is accessed based on an address supplied by either address buffer from the bottom side thereo...

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Bibliographic Details
Main Author OKABAYASHI; ICHIRO
Format Patent
LanguageEnglish
Published 19.03.1996
Edition6
Subjects
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
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Summary:In a memory access device, each of read and write addresses generated by read and write address generating means is stored in a read or write address buffer through a read or write address latch. The memory is accessed based on an address supplied by either address buffer from the bottom side thereof. Each address generating means is arranged such that, when a generated address is stored in the corresponding address buffer, the address calculation stage is finished. Exception detecting means is arranged to conduct exception detection on each address before the address is supplied from the corresponding address buffer, i.e., while the address is being latched by the corresponding address latch. Accordingly, the exception detection on each address can be conducted independently from a pipeline operation, thus shortening the execution time of each calculation stage. This prevents the calculation stage from forming a critical path.
Bibliography:Application Number: US19940322507