Method and apparatus for controlling operation of a cache memory during an interrupt

The use of a high speed cache memory may be selectively controlled when a data processing task is interrupted in response to an interrupt signal, in order to prevent the interrupt from chilling the cache when insufficient performance enhancement will be realized. Disturbing the cache memory during p...

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Bibliographic Details
Main Authors LARSEN; LARRY D, O'DONNELL; KIM E, NUECHTERLEIN; DAVID W, SARTORIUS; THOMAS A, ROGERS; LEE S, SCHULTZ; KENNETH D, LINZER; HARRY I
Format Patent
LanguageEnglish
Published 06.12.1994
Edition5
Subjects
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
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Summary:The use of a high speed cache memory may be selectively controlled when a data processing task is interrupted in response to an interrupt signal, in order to prevent the interrupt from chilling the cache when insufficient performance enhancement will be realized. Disturbing the cache memory during performance of an interrupting task is prevented, thereby increasing the hit ratio of the cache when the interrupted task is resumed. Cache control information may be incorporated into a program status vector or program status word which is loaded into a program status register on occurrence of an interrupt.
Bibliography:Application Number: US19910783551