Random access memory of a CSL system with a bit line pair and an I/O line pair independently set to different precharge voltages

In a dynamic RAM of a CSL system, a memory array is divided into a plurality of memory array portions, and bit line pairs provided in the respective memory array portions are connected to their corresponding I/O line pairs simultaneously in response to a CSL output. In such an RAM, only the I/O line...

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Bibliographic Details
Main Authors TSUKUDE; MASAKI, FUJISHIMA; KAZUYASU, ARIMOTO; KAZUTAMI, HIDAKA; HIDETO, OHISHI; TSUKASA
Format Patent
LanguageEnglish
Published 14.06.1994
Edition5
Subjects
BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
INFORMATION STORAGE
PHYSICS
SEMICONDUCTOR DEVICES
STATIC STORES
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Summary:In a dynamic RAM of a CSL system, a memory array is divided into a plurality of memory array portions, and bit line pairs provided in the respective memory array portions are connected to their corresponding I/O line pairs simultaneously in response to a CSL output. In such an RAM, only the I/O line pair of a memory array portion to be accessed is precharged to the level of VCC-Vth, while the I/O line pair of a memory array portion not to be accessed is precharged to the level of 1/2xVCC which is the same level as the bit line pairs. This makes it possible to achieve a faster data reading operation and also prevent unnecessary currents from flowing between the bit line pairs and the I/O line pair in the unaccessed memory array portion.
Bibliography:Application Number: US19920865145