Process for forming a via in an integrated circuit structure by etching through an insulation layer while inhibiting sputtering of underlying metal

• Main Authors: HILLS; GRAHAM, WU; ROBERT, ARLEO; PAUL, WONG; JERRY, HENRI; JON
• Format: Patent
• Language: English
• Published: 05.01.1993
• Subjects: BASIC ELECTRIC ELEMENTS; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR; ELECTRICITY; SEMICONDUCTOR DEVICES

An improved process is described for forming one or more vias through an insulation layer by plasma etching to an underlying metal layer without depositing etch residues, including metal sputtered from the underlying metal layer, onto the sidewalls of the vias, which comprises, in one embodiment, us...