Planarized thin film surface covered wire bonded semiconductor package

• Main Authors: STARR; STEPHEN G, PAKULSKI; FRANCIS J, IRISH; GARY H, SLATTERY; WILLIAM J, CONRU; H. WARD, WARD; WILLIAM C
• Format: Patent
• Language: English
• Published: 29.09.1992
• Subjects: BASIC ELECTRIC ELEMENTS; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR; ELECTRICITY; SEMICONDUCTOR DEVICES

This is a semiconductor chip in which the conductive path between the chip and the lead frame via wires can be easily and reproduceably improved. This is accomplished by improving the bond between the wires and the lead frame members to which the wires are joined and by creating additional contacts between each wire and its respective lead even if the bonded contact breaks or fails at or immediately adjacent to the bonding point. This is accomplished by placing an insulating layer on the active surface of each chip, carrying input and output bonding pads thereon, to which lead frame conductors have been connected by bonding wires. The insulating layer is a thermosetting adhesive and is placed over the lead frame, the bonding wires and the active face of the semiconductor chip so that when a lamination force is applied to the insulating layer the wires will be crushed and held against their respective pads and against the respective leads to which they are connected and the active face of the semiconductor protected by the adhesive bonding thereto. In this way greater contact between the wires and the leads is enhanced and defects or failure in conductivity therebetween reduced or eliminated.