Logic performance verification and transition fault detection

In scan testing of logic parts, this invention provides an inexpensive transition fault test by changing the sequence of application of the A/C and B clocks. In each machine test cycle the B clock is triggered first, and the A/C clock is triggered second. The periodicity of the clocks is not changed...

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Bibliographic Details
Main Authors VINCENT; BRIAN J, CORR; JAMES L
Format Patent
LanguageEnglish
Published 21.05.1991
Subjects
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