Logic performance verification and transition fault detection
In scan testing of logic parts, this invention provides an inexpensive transition fault test by changing the sequence of application of the A/C and B clocks. In each machine test cycle the B clock is triggered first, and the A/C clock is triggered second. The periodicity of the clocks is not changed...
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Main Authors | , |
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Format | Patent |
Language | English |
Published |
21.05.1991
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Subjects | |
Online Access | Get full text |
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