Logic performance verification and transition fault detection

In scan testing of logic parts, this invention provides an inexpensive transition fault test by changing the sequence of application of the A/C and B clocks. In each machine test cycle the B clock is triggered first, and the A/C clock is triggered second. The periodicity of the clocks is not changed...

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Bibliographic Details
Main Authors VINCENT; BRIAN J, CORR; JAMES L
Format Patent
LanguageEnglish
Published 21.05.1991
Subjects
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
MEASURING
MEASURING ELECTRIC VARIABLES
MEASURING MAGNETIC VARIABLES
PHYSICS
TESTING
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Summary:In scan testing of logic parts, this invention provides an inexpensive transition fault test by changing the sequence of application of the A/C and B clocks. In each machine test cycle the B clock is triggered first, and the A/C clock is triggered second. The periodicity of the clocks is not changed for a particular cycle, because in one cycle the B-to-A/C clocking that naturally occurs provides a minimum test window TP for performance and transition fault testing. Thus, less sophisticated scan test equipment can now provide both transition fault and stuck fault testing, without an increase in complexity or expense.
Bibliography:Application Number: US19890345758