Integrated circuit with complementary MOS transistors

An integrated CMOS circuit comprising a transistor (T2) located in a p (or an n) well (5) and an adjacent complementary transistor (T1). The transistors are located in an epitaxial layer (4) on a highly doped substrate (2). With the use, for example, in bridge circuits having an inductive load, para...

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Bibliographic Details
Main Author LUDIKHUIZE; ADRIANUS W
Format Patent
LanguageEnglish
Published 28.08.1990
Subjects
BASIC ELECTRIC ELEMENTS
CONTROL OR REGULATION OF ELECTRIC MOTORS, ELECTRIC GENERATORSOR DYNAMO-ELECTRIC CONVERTERS
CONTROLLING TRANSFORMERS, REACTORS OR CHOKE COILS
CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
GENERATION
SEMICONDUCTOR DEVICES
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Summary:An integrated CMOS circuit comprising a transistor (T2) located in a p (or an n) well (5) and an adjacent complementary transistor (T1). The transistors are located in an epitaxial layer (4) on a highly doped substrate (2). With the use, for example, in bridge circuits having an inductive load, parasitic currents can occur, which give rise to "latch-up" and/or dissipation. According to the invention, this can be avoided in that under the source zone of the transistor (T1) located beside the well is provided a second region having substantially the same doping and depth as the well, which is connected to the said source zone.
Bibliography:Application Number: US19890334963