Method for making metal contact studs between first level metal and regions of a semiconductor device compatible with polyimide-filled deep trench isolation schemes

• Main Authors: GALIE; JOHN R, GOTH; GEORGE R, VILLETTO, JR.; ROBERT T, HANSEN; THOMAS A
• Format: Patent
• Language: English
• Published: 17.09.1985
• Edition: 4
• Subjects: BASIC ELECTRIC ELEMENTS; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR; ELECTRICITY; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; SEMICONDUCTOR DEVICES; TECHNICAL SUBJECTS COVERED BY FORMER USPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ARTCOLLECTIONS [XRACs] AND DIGESTS

The present method discloses the steps to form metal device contact studs between regions of a semiconductor device, such as an NPN vertical bipolar transistor, and the first level metal, the studs overlapping both a contact region (such as the base or the collector) and an adjacent polyimide-filled trench. The method is comprised of the following steps: (a) applying a lift off mask exposing said contact region and adjacent trench without attacking the polyimide fill, (b) blanket depositing the stud forming metal onto the whole structure, (c) lifting off said mask and the overlying metal, (d) blanket depositing a second dielectric layer onto the whole structure, the thickness of said second layer being approximately the stud height, (e) removing said second dielectric layer until the top surface of the highest contact stud is exposed and (f) polishing both the metal and said second dielectric layer to leave a substantially planarized structure ready for further personalization.