Method and circuit arrangement for controlling an integrated semiconductor memory

• Main Authors: HEUBER; KLAUS, WIEDMANN; SIEGFRIED K
• Format: Patent
• Language: English
• Published: 21.07.1981
• Subjects: BASIC ELECTRIC ELEMENTS; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR; ELECTRICITY; INFORMATION STORAGE; PHYSICS; SEMICONDUCTOR DEVICES; STATIC STORES

In integrated semiconductor memory cell arrangements, particularly integrated semiconductor memory cell arrangements using merged transistor logic configurations, line capacitances are discharged before accessing to reduce access time and power consumption. Individual bit line transistor switching m...