Method and circuit arrangement for controlling an integrated semiconductor memory

• Main Authors: HEUBER; KLAUS, WIEDMANN; SIEGFRIED K
• Format: Patent
• Language: English
• Published: 21.07.1981
• Subjects: BASIC ELECTRIC ELEMENTS; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR; ELECTRICITY; INFORMATION STORAGE; PHYSICS; SEMICONDUCTOR DEVICES; STATIC STORES

In integrated semiconductor memory cell arrangements, particularly integrated semiconductor memory cell arrangements using merged transistor logic configurations, line capacitances are discharged before accessing to reduce access time and power consumption. Individual bit line transistor switching means are coupled to each bit line to provide a discharge path for the line capacitances associated therewith. Common transistor switching means are coupled to each individual bit line transistor switching means to commonly discharge the individual discharge currents received from each individual bit line transistor switching means. Individual word line transistor switching means are also connected to respective word lines to distribute the current passing through the common transistor switching means to the respective word lines. The discharge circuit arrangement permits minimum-area bit line and word line transistor switching means.