MEMORY CONTROLLER AND MEMORY SYSTEM WITH DATA STROBE SIGNAL CALIBRATION CIRCUIT
In some embodiments of the disclosed technology, a memory controller may include a data strobe signal (DQS) calibration circuit configured to calibrate timing of a data strobe signal (DQS) for a plurality of memory dies by performing N unit DQS calibration operations, wherein N is a natural number,...
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Main Author | |
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Format | Patent |
Language | English |
Published |
12.09.2024
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Subjects | |
Online Access | Get full text |
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Summary: | In some embodiments of the disclosed technology, a memory controller may include a data strobe signal (DQS) calibration circuit configured to calibrate timing of a data strobe signal (DQS) for a plurality of memory dies by performing N unit DQS calibration operations, wherein N is a natural number, wherein performing the N unit DQS calibration operations includes: performing M unit DQS calibration operations in a normal mode on the plurality of memory dies, wherein M is a natural number smaller than N; upon failure of calibration during the M unit DQS calibration operations in the normal mode, determining a representative memory die of the plurality of memory dies that causes the failure of calibration; and performing N−M unit DQS calibration operations in a conditional mode on the plurality of memory dies by varying parameters associated with the representative memory die of the plurality of memory dies. |
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Bibliography: | Application Number: US202318469394 |