Semiconductor Structure Having High Breakdown Voltage Etch-Stop Layer
The present disclosure relates to a method of forming a semiconductor structure. The method includes depositing an etch-stop layer (ESL) over a first dielectric layer. The ESL layer deposition can include: flowing a first precursor over the first dielectric layer; purging at least a portion of the f...
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Main Authors | , |
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Format | Patent |
Language | English |
Published |
08.08.2024
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Subjects | |
Online Access | Get full text |
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