MIDDLE OF LINE DIELECTRIC LAYER ENGINEERING FOR VIA VOID PREVENTION

Embodiments of the present disclosure are provide a method for fabricating a semiconductor device with fewer via voids (e.g., gaps between a dielectric layer and a metal fill of the semiconductor device). One such technique involves forming a dielectric layer, wherein at least a portion of the diele...

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Bibliographic Details
Main Authors BREIL, Nicolas Louis, PRANATHARTHIHARAN, Balasubramanian, MALLICK, Abhijit B
Format Patent
LanguageEnglish
Published 28.03.2024
Subjects
BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
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Summary:Embodiments of the present disclosure are provide a method for fabricating a semiconductor device with fewer via voids (e.g., gaps between a dielectric layer and a metal fill of the semiconductor device). One such technique involves forming a dielectric layer, wherein at least a portion of the dielectric layer comprises a nonstoichiometric compound; forming one or more openings in the dielectric layer; filling the one or more openings with a metal, wherein the metal is disposed on a surface of each of the one or more openings; and exposing the dielectric layer and metal disposed in the openings to an oxidizing atmosphere, wherein exposing the dielectric layer and metal in the openings causes oxidation of the nonstoichiometric compound.
Bibliography:Application Number: US202318472062