HIGH PERFORMANCE INTERCONNECT
A physical layer (PHY) is coupled to a serial, differential link that is to include a number of lanes. The PHY includes a transmitter and a receiver to be coupled to each lane of the number of lanes. The transmitter coupled to each lane is configured to embed a clock with data to be transmitted over...
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Main Authors | , , , , , , , , , , , , , , , , , , , , , , , |
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Format | Patent |
Language | English |
Published |
11.01.2024
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Subjects | |
Online Access | Get full text |
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Abstract | A physical layer (PHY) is coupled to a serial, differential link that is to include a number of lanes. The PHY includes a transmitter and a receiver to be coupled to each lane of the number of lanes. The transmitter coupled to each lane is configured to embed a clock with data to be transmitted over the lane, and the PHY periodically issues a blocking link state (BLS) request to cause an agent to enter a BLS to hold off link layer flit transmission for a duration. The PHY utilizes the serial, differential link during the duration for a PHY associated task selected from a group including an in-band reset, an entry into low power state, and an entry into partial width state. |
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AbstractList | A physical layer (PHY) is coupled to a serial, differential link that is to include a number of lanes. The PHY includes a transmitter and a receiver to be coupled to each lane of the number of lanes. The transmitter coupled to each lane is configured to embed a clock with data to be transmitted over the lane, and the PHY periodically issues a blocking link state (BLS) request to cause an agent to enter a BLS to hold off link layer flit transmission for a duration. The PHY utilizes the serial, differential link during the duration for a PHY associated task selected from a group including an in-band reset, an entry into low power state, and an entry into partial width state. |
Author | Johnson, Simon P Beers, Robert Jue, Darren S Spink, Aaron T Blankenship, Robert G Ramanujan, Raj K Swanson, Jeffrey C Iyer, Sitaraman V Safranek, Robert J Das, Abhishek Dhillon, Yuvraj S Kumar, Arvind A Shah, Rahul R Hum, Herbert H Spagna, Fulvio Geetha, Vedaraman Nale, William Harry Fahim, Bahaa Maddox, Robert A Iyer, Venkatraman Das Sharma, Debendra Gupta, Ashish Willey, Jeff Liu, Yen-Cheng |
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Snippet | A physical layer (PHY) is coupled to a serial, differential link that is to include a number of lanes. The PHY includes a transmitter and a receiver to be... |
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SubjectTerms | CALCULATING COMPUTING COUNTING ELECTRIC COMMUNICATION TECHNIQUE ELECTRIC DIGITAL DATA PROCESSING ELECTRICITY PHYSICS TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHICCOMMUNICATION |
Title | HIGH PERFORMANCE INTERCONNECT |
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