Rule compilation schemes for fast packet classification

A classification apparatus includes a memory and a processor. The memory is configured to store rules corresponding to a corpus of rules in respective rule entries, each rule includes a respective set of unmasked bits having corresponding bit values, and at least some of the rules include masked bit...

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Bibliographic Details
Main Authors Urman, Avi, Bar Yanai, Roni, Levy, Gil
Format Patent
LanguageEnglish
Published 24.08.2023
Subjects
CALCULATING
COMPUTING
COUNTING
ELECTRIC COMMUNICATION TECHNIQUE
ELECTRIC DIGITAL DATA PROCESSING
ELECTRICITY
PHYSICS
TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHICCOMMUNICATION
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Summary:A classification apparatus includes a memory and a processor. The memory is configured to store rules corresponding to a corpus of rules in respective rule entries, each rule includes a respective set of unmasked bits having corresponding bit values, and at least some of the rules include masked bits. The rules in the corpus conform to respective Rule Patterns (RPs), each RP defining a respective sequence of masked and unmasked bits. The processor is configured to cluster the RPs, using a clustering criterion, into extended Rule Patterns (eRPs) associated with respective hash tables including buckets for storing rule entries. The clustering criterion aims to minimize an overall number of the eRPs while meeting a collision condition that depends on a specified maximal number of rule entries per bucket.
Bibliography:Application Number: US202217678074