Priority-Based Cache-Line Fitting in Compressed Memory Systems of Processor-Based Systems

• Main Authors: CHHABRA, Gurvinder Singh, GENG, Norris, SENIOR, Richard, WANG, Kan
• Format: Patent
• Language: English
• Published: 27.07.2023
• Subjects: CALCULATING; COMPUTING; COUNTING; ELECTRIC DIGITAL DATA PROCESSING; PHYSICS

A compressed memory system of a processor-based system includes a memory partitioning circuit for partitioning a memory region into data regions with different priority levels. The system also includes a cache line selection circuit for selecting a first cache line from a high priority data region a...