SECURE KEY EXCHANGE IN A MULTI-PROCESSOR DEVICE

An integrated circuit comprises an interface controller to receive a message, wherein at least a portion of the message is encrypted, a primary processor coupled to the interface controller and configured to process the received message, and a secondary secure processor coupled to the primary proces...

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Bibliographic Details
Main Authors Wu, Winthrop John, Wittenauer, Joel, Erickson, Evan Lawrence
Format Patent
LanguageEnglish
Published 25.05.2023
Subjects
ELECTRIC COMMUNICATION TECHNIQUE
ELECTRICITY
TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHICCOMMUNICATION
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Summary:An integrated circuit comprises an interface controller to receive a message, wherein at least a portion of the message is encrypted, a primary processor coupled to the interface controller and configured to process the received message, and a secondary secure processor coupled to the primary processor and to the interface controller. The secondary secure processor is configured to decrypt the portion of the message that is encrypted on behalf of the primary processor, analyze the decrypted portion of the message to determine whether the decrypted portion comprises information pertaining to sensitive data, and responsive to determining that the decrypted portion comprises information pertaining to sensitive data, process the information pertaining to the sensitive data and provide the sensitive data to the interface controller via a secure private bus not accessible by the primary processor.
Bibliography:Application Number: US202217990417