TWO-SIDED INTERCONNECTED EMBEDDED CHIP PACKAGING STRUCTURE AND MANUFACTURING METHOD THEREFOR

• Main Authors: HONG, Yejie, FENG, Jindong, CHEN, Xianming, HUANG, Benxia
• Format: Patent
• Language: English
• Published: 18.05.2023
• Subjects: BASIC ELECTRIC ELEMENTS; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR; ELECTRICITY; SEMICONDUCTOR DEVICES

A two-sided interconnected embedded chip packaging structure includes a first insulating layer and a second insulating layer. The first insulating layer includes a first conductive copper column layer penetrating through the first insulating layer in a height direction and a first chip located between adjacent first conductive copper columns, and the first chip is attached to the inside of the lower surface of the first insulating layer. The second insulating layer includes a first conductive wire layer and a heat radiation copper surface which are located in the upper surface of the second insulating layer, the first conductive wire layer is provided with a second conductive copper column layer, the first conductive copper column layer is connected with the first conductive wire layer, and the heat radiation copper surface is connected with the reverse side of the first chip.