Integrated Circuit and Method for Protecting an Integrated Circuit Against Reverse Engineering

A bit generation circuit having a plurality of signal chains, where for each chain, a first input of an input multiplexer is connected to another of the signal chains and the multiplexer is configured so that, if a control signal indicating a normal operating mode is fed to the multiplexer, the mult...

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Bibliographic Details
Main Authors Wroblewski, Artur, Seidl, Stefan, Hatsch, Joel
Format Patent
LanguageEnglish
Published 18.05.2023
Subjects
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
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Summary:A bit generation circuit having a plurality of signal chains, where for each chain, a first input of an input multiplexer is connected to another of the signal chains and the multiplexer is configured so that, if a control signal indicating a normal operating mode is fed to the multiplexer, the multiplexer connects the first input to the path input of the signal chain. The second input of each multiplexer is connected to the output of a bit generation trigger circuit and, for each signal chain, the multiplexer is configured so that, if a control signal indicating a secret generation mode is fed to the multiplexer, it connects the second input to the path input of the signal chain. The bit generation circuit furthermore comprises an arbiter circuit connected to the path outputs of at least two signal chains and configured to output a secret bit depending on their states.
Bibliography:Application Number: US202217983839