SEQUENTIAL WORDLINE ERASE VERIFY SCHEMES

A memory device includes a memory array including a plurality of wordline groups, each wordline group of the plurality of wordline groups including a set of even wordlines and a set of odd wordlines, and control logic, operatively coupled with the memory array, to perform operations including identi...

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Bibliographic Details
Main Authors Yin, Chengkuan, Sato, Shinji, Lai, Jiun-Horng, Prakash, Ronit Roneel
Format Patent
LanguageEnglish
Published 20.04.2023
Subjects
INFORMATION STORAGE
PHYSICS
STATIC STORES
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Summary:A memory device includes a memory array including a plurality of wordline groups, each wordline group of the plurality of wordline groups including a set of even wordlines and a set of odd wordlines, and control logic, operatively coupled with the memory array, to perform operations including identifying a set of failing wordline groups from the plurality of wordline groups, the set of failing wordline groups including at least one failing wordline group determined to have failed a first erase verify of an erase verify process, and causing a second erase verify of the erase verify process to be performed sequentially with respect to each failing wordline group of the set of failing wordline groups.
Bibliography:Application Number: US202218085783