METHOD TO PRODUCE 3D SEMICONDUCTOR DEVICES AND STRUCTURES WITH MEMORY
A method for producing a 3D semiconductor device including: providing a first level, the first level including a first single crystal layer; forming first alignment marks and control circuits in and/or on the first level, where the control circuits include first single crystal transistors and at lea...
Saved in:
Main Authors | , |
---|---|
Format | Patent |
Language | English |
Published |
23.02.2023
|
Subjects | |
Online Access | Get full text |
Cover
Loading…
Abstract | A method for producing a 3D semiconductor device including: providing a first level, the first level including a first single crystal layer; forming first alignment marks and control circuits in and/or on the first level, where the control circuits include first single crystal transistors and at least two interconnection metal layers; forming at least one second level disposed above the control circuits; performing a first etch step into the second level; forming at least one third level disposed on top of the second level; performing additional processing steps to form first memory cells within the second level and second memory cells within the third level, where each of the first memory cells include at least one second transistor, where each of the second memory cells include at least one third transistor, performing bonding of the first level to the second level, where the bonding includes oxide to oxide bonding. |
---|---|
AbstractList | A method for producing a 3D semiconductor device including: providing a first level, the first level including a first single crystal layer; forming first alignment marks and control circuits in and/or on the first level, where the control circuits include first single crystal transistors and at least two interconnection metal layers; forming at least one second level disposed above the control circuits; performing a first etch step into the second level; forming at least one third level disposed on top of the second level; performing additional processing steps to form first memory cells within the second level and second memory cells within the third level, where each of the first memory cells include at least one second transistor, where each of the second memory cells include at least one third transistor, performing bonding of the first level to the second level, where the bonding includes oxide to oxide bonding. |
Author | Sekar, Deepak C Or-Bach, Zvi |
Author_xml | – fullname: Or-Bach, Zvi – fullname: Sekar, Deepak C |
BookMark | eNrjYmDJy89L5WRw9XUN8fB3UQjxVwgI8ncJdXZVMHZRCHb19XT29wNyQ_yDFFxcwzydXYMVHP2AMiFBQMHQICA33DPEQ8HX1dc_KJKHgTUtMac4lRdKczMou7mGOHvophbkx6cWFyQmp-allsSHBhsZGBkbmJoZm5g5GhoTpwoAXbUu1w |
ContentType | Patent |
DBID | EVB |
DatabaseName | esp@cenet |
DatabaseTitleList | |
Database_xml | – sequence: 1 dbid: EVB name: esp@cenet url: http://worldwide.espacenet.com/singleLineSearch?locale=en_EP sourceTypes: Open Access Repository |
DeliveryMethod | fulltext_linktorsrc |
Discipline | Medicine Chemistry Sciences |
ExternalDocumentID | US2023056346A1 |
GroupedDBID | EVB |
ID | FETCH-epo_espacenet_US2023056346A13 |
IEDL.DBID | EVB |
IngestDate | Fri Oct 04 05:01:43 EDT 2024 |
IsOpenAccess | true |
IsPeerReviewed | false |
IsScholarly | false |
Language | English |
LinkModel | DirectLink |
MergedId | FETCHMERGED-epo_espacenet_US2023056346A13 |
Notes | Application Number: US202217898475 |
OpenAccessLink | https://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20230223&DB=EPODOC&CC=US&NR=2023056346A1 |
ParticipantIDs | epo_espacenet_US2023056346A1 |
PublicationCentury | 2000 |
PublicationDate | 20230223 |
PublicationDateYYYYMMDD | 2023-02-23 |
PublicationDate_xml | – month: 02 year: 2023 text: 20230223 day: 23 |
PublicationDecade | 2020 |
PublicationYear | 2023 |
RelatedCompanies | Monolithic 3D Inc |
RelatedCompanies_xml | – name: Monolithic 3D Inc |
Score | 3.4540675 |
Snippet | A method for producing a 3D semiconductor device including: providing a first level, the first level including a first single crystal layer; forming first... |
SourceID | epo |
SourceType | Open Access Repository |
SubjectTerms | BASIC ELECTRIC ELEMENTS ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY SEMICONDUCTOR DEVICES |
Title | METHOD TO PRODUCE 3D SEMICONDUCTOR DEVICES AND STRUCTURES WITH MEMORY |
URI | https://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20230223&DB=EPODOC&locale=&CC=US&NR=2023056346A1 |
hasFullText | 1 |
inHoldings | 1 |
isFullTextHit | |
isPrint | |
link | http://utb.summon.serialssolutions.com/2.0.0/link/0/eLvHCXMwfR1dS8MwMIwp6ptOxY8pAaVvRTRNPx6GbElGJ7QZbTrn02jXFgTphqv4973GTfe0t-QOjsuFy-VyuTuE7uclTWGrLdPzKGnCjNRMU4-YNCVpmedOaet2PkFo-4n1MqXTFvrY5MLoOqHfujgiaNQc9L3W5_Xy_xGL67-Vq4fsHUCL56HqcWPtHcN9GsydwQc9MZZcMoOxXhIbYfSLozax7D74SntwkXYafRCTQZOXstw2KsNjtD8GelV9glpF1UGHbNN7rYMOgnXIG4Zr7VudIhEI5UuOlcTjSPKECUw4jhtJyhCmSkaYi8mIiRj3Q8CoCIAJyBi_jpSPAxHI6O0M3Q2FYr4J_Mz-lj9L4m3myTlqV4uquEDYtUv6lLvW3LU9ixa5l7qpZ2WPpePkGbhVl6i7i9LVbvQ1OmqmOn2bdFG7_vwqbsAA19mtltsP0vSChA |
link.rule.ids | 230,309,783,888,25576,76876 |
linkProvider | European Patent Office |
linkToHtml | http://utb.summon.serialssolutions.com/2.0.0/link/0/eLvHCXMwfR1dS8NALIwp6ptOxY-pB0rfimh7_XgYsvVudLr2Rnud82m0awuCdMNV_PumddM97e3uAiGXI5fkckkA7mY5jfGoddW2qVaFGakax7am0liL8zQ1c6Nu5-P5hhvpzxM6acDHOhemrhP6XRdHRImaobyX9X29-H_EYvXfyuV98o5L86e-7DBl5R2jPY3qTmG9Dh8JJhzFcTpRqPjBL4wamm500VfaQSPbrOSBj3tVXspiU6n0D2F3hPiK8ggaWdGCfWfde60Fe94q5I3DlfQtj4F7XLqCESnIKBAscjjRGAkrTgofp1IEhPHxwOEh6foIkQEuRshj8jqQLvG4J4K3E7jtc-m4KtIz_dv-NAo3iddOoVnMi-wMiGXk9DG19Jll2DrNUju2YltPHnLTTBN0q86hvQ3TxXbwDey70htOhwP_5RIOKlCdyq21oVl-fmVXqIzL5Lrm4Q8eK4V3 |
openUrl | ctx_ver=Z39.88-2004&ctx_enc=info%3Aofi%2Fenc%3AUTF-8&rfr_id=info%3Asid%2Fsummon.serialssolutions.com&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Apatent&rft.title=METHOD+TO+PRODUCE+3D+SEMICONDUCTOR+DEVICES+AND+STRUCTURES+WITH+MEMORY&rft.inventor=Or-Bach%2C+Zvi&rft.inventor=Sekar%2C+Deepak+C&rft.date=2023-02-23&rft.externalDBID=A1&rft.externalDocID=US2023056346A1 |