VIA LANDING ON FIRST AND SECOND BARRIER LAYERS TO REDUCE CLEANING TIME OF CONDUCTIVE STRUCTURE

• Main Authors: Hsieh, Te-Hsien, Chang, Yu-Hsing, Chen, Yi-Min
• Format: Patent
• Language: English
• Published: 15.09.2022
• Subjects: BASIC ELECTRIC ELEMENTS; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR; ELECTRICITY; SEMICONDUCTOR DEVICES

In some embodiments, the present disclosure relates to an integrated chip that includes a conductive structure arranged within a substrate or a first dielectric layer. A first barrier layer is arranged on outermost sidewalls and a bottom surface of the conductive structure. A second barrier layer is arranged on outer surfaces of the first barrier layer. The second barrier layer separates the first barrier layer from the substrate or the first dielectric layer. A second dielectric layer is arranged over the substrate or the first dielectric layer. A via structure extends through the second dielectric layer, is arranged directly over topmost surfaces of the first and second barrier layers, and is electrically coupled to the conductive structure through the first and second barrier layers.