METHODS OF DESIGNING LAYOUT OF SEMICONDUCTOR DEVICE AND METHODS FOR MANUFACTURING SEMICONDUCTOR DEVICE USING THE SAME
A method of designing a layout of a semiconductor device, includes: preparing a standard cell library including information on standard cells; determining a layout of a common pattern region in consideration of a local layout effect based on the standard cell library; adding the common pattern regio...
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Main Author | |
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Format | Patent |
Language | English |
Published |
21.07.2022
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Subjects | |
Online Access | Get full text |
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Summary: | A method of designing a layout of a semiconductor device, includes: preparing a standard cell library including information on standard cells; determining a layout of a common pattern region in consideration of a local layout effect based on the standard cell library; adding the common pattern region having a cell height that is identical to a cell height of each of the standard cells to opposite sides of one or more of the standard cells; and arranging the standard cells to share the common pattern region between at least one pair of adjacent ones of the standard cells. |
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Bibliography: | Application Number: US202117517126 |