TEST PAD STRUCTURE OF CHIP

The present invention provides a test pad structure of chip, which comprises a plurality of first internal test pads, a plurality of second internal test pads, a plurality of first extended test pads, and a plurality of second extended test pads. The first internal test pads and the second internal...

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Main Authors TSENG, KUO-WEI, CHEN, POI
Format Patent
LanguageEnglish
Published 03.02.2022
Subjects
BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
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Abstract The present invention provides a test pad structure of chip, which comprises a plurality of first internal test pads, a plurality of second internal test pads, a plurality of first extended test pads, and a plurality of second extended test pads. The first internal test pads and the second internal test pads are disposed in a chip. The second internal test pads and the first internal test pads are spaced by a distance. The first extended test pads are connected with the first internal test pads. The second extended test pads are connected with the second internal test pads. The first extended test pads and the second extended test pads may increase the contact area to be contacted by probes. Signals or power are transmitted to the first internal test pads and the second internal test pads via the first extended test pads and the second extended test pads for the probes to test the chip.
AbstractList The present invention provides a test pad structure of chip, which comprises a plurality of first internal test pads, a plurality of second internal test pads, a plurality of first extended test pads, and a plurality of second extended test pads. The first internal test pads and the second internal test pads are disposed in a chip. The second internal test pads and the first internal test pads are spaced by a distance. The first extended test pads are connected with the first internal test pads. The second extended test pads are connected with the second internal test pads. The first extended test pads and the second extended test pads may increase the contact area to be contacted by probes. Signals or power are transmitted to the first internal test pads and the second internal test pads via the first extended test pads and the second extended test pads for the probes to test the chip.
Author TSENG, KUO-WEI
CHEN, POI
Author_xml – fullname: TSENG, KUO-WEI
– fullname: CHEN, POI
BookMark eNrjYmDJy89L5WSQCnENDlEIcHRRCA4JCnUOCQ1yVfB3U3D28AzgYWBNS8wpTuWF0twMym6uIc4euqkF-fGpxQWJyal5qSXxocFGBkZGBsbmRoYWjobGxKkCAH_BIsg
ContentType Patent
DBID EVB
DatabaseName esp@cenet
DatabaseTitleList
Database_xml – sequence: 1
  dbid: EVB
  name: esp@cenet
  url: http://worldwide.espacenet.com/singleLineSearch?locale=en_EP
  sourceTypes: Open Access Repository
DeliveryMethod fulltext_linktorsrc
Discipline Medicine
Chemistry
Sciences
ExternalDocumentID US2022037218A1
GroupedDBID EVB
ID FETCH-epo_espacenet_US2022037218A13
IEDL.DBID EVB
IngestDate Fri Jul 19 12:50:19 EDT 2024
IsOpenAccess true
IsPeerReviewed false
IsScholarly false
Language English
LinkModel DirectLink
MergedId FETCHMERGED-epo_espacenet_US2022037218A13
Notes Application Number: US202117444233
OpenAccessLink https://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20220203&DB=EPODOC&CC=US&NR=2022037218A1
ParticipantIDs epo_espacenet_US2022037218A1
PublicationCentury 2000
PublicationDate 20220203
PublicationDateYYYYMMDD 2022-02-03
PublicationDate_xml – month: 02
  year: 2022
  text: 20220203
  day: 03
PublicationDecade 2020
PublicationYear 2022
RelatedCompanies SITRONIX TECHNOLOGY CORP
RelatedCompanies_xml – name: SITRONIX TECHNOLOGY CORP
Score 3.3857472
Snippet The present invention provides a test pad structure of chip, which comprises a plurality of first internal test pads, a plurality of second internal test pads,...
SourceID epo
SourceType Open Access Repository
SubjectTerms BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
Title TEST PAD STRUCTURE OF CHIP
URI https://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20220203&DB=EPODOC&locale=&CC=US&NR=2022037218A1
hasFullText 1
inHoldings 1
isFullTextHit
isPrint
link http://utb.summon.serialssolutions.com/2.0.0/link/0/eLvHCXMwfV3dS8MwED_GFPVNp6JzSkHpW3H046wPRba0pQpby9rK3kbTpiDIHK7iv-8ldrqnvSU5uHzA5fLLfQHcYV2Y3EVhiOGwNmyBaBBWsQ0SK5eXLkeuSidMphjl9svcmXfgfRMLo_KEfqvkiCRRJcl7o-7r1f8nlq98K9f3_I2GPp7CzPP1Fh2bpjSs6f7YC5LYj5nOmJen-nT2S7MI7rgjwkp78iEtM-0Hr2MZl7LaVirhMewnxG_ZnEBHLHtwyDa113pwMGlN3tRspW99Cv0sSDMtGflams1yJh0WtDjUWPScnMFtGGQsMmiSxd-eFnm6vSLrHLqE9sUFaCWpYKwQHUGPG2EVjyU-8Lqo0K4ciWMvYbCLU383-QqOZFe5HVsD6DafX-KatGrDb9Rh_ABklnZL
link.rule.ids 230,309,786,891,25594,76903
linkProvider European Patent Office
linkToHtml http://utb.summon.serialssolutions.com/2.0.0/link/0/eLvHCXMwfV1LS8NAEB5KFetNq2Jr1YCSW7DksY2HIO0mIdXmQZNIb6GbbECQWmzEv-9kTbWn3pYdmH3At7Pf7jwA7km5VJlJuMKHw1LROSEKchVdQViZLDcZYaJ0gh8QL9WfF8aiBe_bWBiRJ_RbJEdEROWI90qc1-v_Ryxb-FZuHtgbdn08uYllyw07VtX6Y022J5YThXZIZUqtNJaD-a9MQ7pjjpErHYyQFAqy9Dqp41LWu0bFPYHDCPWtqlNo8VUXOnRbe60LR37z5Y3NBn2bM-gnTpxI0diW4mSe0tphQQpdiXrT6BzuXCehnoKDZH9rytJ4d0baBbSR7fNLkHI0waQgxOB4ueHa8jEnI1YuC6IXRs1jezDYp6m_X3wLHS_xZ9lsGrxcwXEtEi7I2gDa1ecXv0YLW7EbsTE_EYx5NQ
openUrl ctx_ver=Z39.88-2004&ctx_enc=info%3Aofi%2Fenc%3AUTF-8&rfr_id=info%3Asid%2Fsummon.serialssolutions.com&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Apatent&rft.title=TEST+PAD+STRUCTURE+OF+CHIP&rft.inventor=TSENG%2C+KUO-WEI&rft.inventor=CHEN%2C+POI&rft.date=2022-02-03&rft.externalDBID=A1&rft.externalDocID=US2022037218A1