DISTRIBUTED GROUPED TERMINATIONS FOR MULTIPLE MEMORY INTEGRATED CIRCUIT SYSTEMS

• Main Authors: Contreras, John Thomas, Mobin, Sayed, Rajendra, Srinivas, Zakai, Rehan Ahmed
• Format: Patent
• Language: English
• Published: 30.12.2021
• Subjects: BASIC ELECTRIC ELEMENTS; BASIC ELECTRONIC CIRCUITRY; CALCULATING; COMPUTING; COUNTING; ELECTRIC DIGITAL DATA PROCESSING; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR; ELECTRICITY; INFORMATION STORAGE; PHYSICS; PULSE TECHNIQUE; SEMICONDUCTOR DEVICES; STATIC STORES

The disclosed apparatuses and method provide transmission line termination. An apparatus include a stack of uniform memory dies and a storage controller. Each uniform memory die in the stack of uniform memory dies couples to a transmission line in series through wire bonds to form a transmission path. Each memory die includes an on-die termination resistance circuit connected to the transmission line. The on-die termination resistance circuit provides a minimum termination resistance. The storage controller addresses a target uniform memory die of the for an operation. The storage controller enables the on-die termination resistance circuits of a plurality of uniform memory dies along the transmission path. The storage controller transmits a data signal for the operation to the target uniform memory die with the on-die termination resistance circuit enabled for the plurality of uniform memory dies.