DISTRIBUTED GROUPED TERMINATIONS FOR MULTIPLE MEMORY INTEGRATED CIRCUIT SYSTEMS
The disclosed apparatuses and method provide transmission line termination. An apparatus include a stack of uniform memory dies and a storage controller. Each uniform memory die in the stack of uniform memory dies couples to a transmission line in series through wire bonds to form a transmission pat...
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Format | Patent |
Language | English |
Published |
30.12.2021
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Abstract | The disclosed apparatuses and method provide transmission line termination. An apparatus include a stack of uniform memory dies and a storage controller. Each uniform memory die in the stack of uniform memory dies couples to a transmission line in series through wire bonds to form a transmission path. Each memory die includes an on-die termination resistance circuit connected to the transmission line. The on-die termination resistance circuit provides a minimum termination resistance. The storage controller addresses a target uniform memory die of the for an operation. The storage controller enables the on-die termination resistance circuits of a plurality of uniform memory dies along the transmission path. The storage controller transmits a data signal for the operation to the target uniform memory die with the on-die termination resistance circuit enabled for the plurality of uniform memory dies. |
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AbstractList | The disclosed apparatuses and method provide transmission line termination. An apparatus include a stack of uniform memory dies and a storage controller. Each uniform memory die in the stack of uniform memory dies couples to a transmission line in series through wire bonds to form a transmission path. Each memory die includes an on-die termination resistance circuit connected to the transmission line. The on-die termination resistance circuit provides a minimum termination resistance. The storage controller addresses a target uniform memory die of the for an operation. The storage controller enables the on-die termination resistance circuits of a plurality of uniform memory dies along the transmission path. The storage controller transmits a data signal for the operation to the target uniform memory die with the on-die termination resistance circuit enabled for the plurality of uniform memory dies. |
Author | Mobin, Sayed Rajendra, Srinivas Contreras, John Thomas Zakai, Rehan Ahmed |
Author_xml | – fullname: Contreras, John Thomas – fullname: Mobin, Sayed – fullname: Rajendra, Srinivas – fullname: Zakai, Rehan Ahmed |
BookMark | eNqNy70KwjAUQOEMOvj3DgFnoa1W55je1gtNU25uhk6lSJwkLdT3RwUfwOlbzlmLRRxjWAlboGPCq2coZEXWtx8ZyGCjGG3jZGlJGl8ztjVIA8ZSJ7FhqEh9H42kPbJ0nWMwbiuWj-E5h93PjdiXwPp2CNPYh3ka7iGGV-9dlmTpKbnk51ylx_-qN5sSMjw |
ContentType | Patent |
DBID | EVB |
DatabaseName | esp@cenet |
DatabaseTitleList | |
Database_xml | – sequence: 1 dbid: EVB name: esp@cenet url: http://worldwide.espacenet.com/singleLineSearch?locale=en_EP sourceTypes: Open Access Repository |
DeliveryMethod | fulltext_linktorsrc |
Discipline | Medicine Chemistry Sciences Physics |
ExternalDocumentID | US2021407565A1 |
GroupedDBID | EVB |
ID | FETCH-epo_espacenet_US2021407565A13 |
IEDL.DBID | EVB |
IngestDate | Fri Jul 19 15:18:41 EDT 2024 |
IsOpenAccess | true |
IsPeerReviewed | false |
IsScholarly | false |
Language | English |
LinkModel | DirectLink |
MergedId | FETCHMERGED-epo_espacenet_US2021407565A13 |
Notes | Application Number: US202016916945 |
OpenAccessLink | https://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20211230&DB=EPODOC&CC=US&NR=2021407565A1 |
ParticipantIDs | epo_espacenet_US2021407565A1 |
PublicationCentury | 2000 |
PublicationDate | 20211230 |
PublicationDateYYYYMMDD | 2021-12-30 |
PublicationDate_xml | – month: 12 year: 2021 text: 20211230 day: 30 |
PublicationDecade | 2020 |
PublicationYear | 2021 |
RelatedCompanies | Western Digital Technologies, Inc |
RelatedCompanies_xml | – name: Western Digital Technologies, Inc |
Score | 3.3796895 |
Snippet | The disclosed apparatuses and method provide transmission line termination. An apparatus include a stack of uniform memory dies and a storage controller. Each... |
SourceID | epo |
SourceType | Open Access Repository |
SubjectTerms | BASIC ELECTRIC ELEMENTS BASIC ELECTRONIC CIRCUITRY CALCULATING COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY INFORMATION STORAGE PHYSICS PULSE TECHNIQUE SEMICONDUCTOR DEVICES STATIC STORES |
Title | DISTRIBUTED GROUPED TERMINATIONS FOR MULTIPLE MEMORY INTEGRATED CIRCUIT SYSTEMS |
URI | https://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20211230&DB=EPODOC&locale=&CC=US&NR=2021407565A1 |
hasFullText | 1 |
inHoldings | 1 |
isFullTextHit | |
isPrint | |
link | http://utb.summon.serialssolutions.com/2.0.0/link/0/eLvHCXMwfZ3fa4MwEMeP0v1827qN_ehGYMM3WYux1ocyarSro6nF6GifiloHg2HL6ti_v0tmtz71SUxI0MDl7qN33wA8ICTnJm0nurWwWjq1zEzvJpmhmwltdy0jR5cui5P5uDOM6cvUnNbgY1MLo3RCv5U4IlpUhvZeqv169f8Ry1W5levH9B2blk-DqOdqFR0jzWBIrblOz5sEbsA0xnqx0Mah6kN2wfClj6y0JwNpqbTvvTqyLmW17VQGJ7A_wfmK8hRqedGAI7Y5e60Bh7z65d2AA5Wjma2xsbLD9RkEri-i0Hdi3HeIypzHKwam3P9VtxUE4Y7weBT5k5FHuMeDcEak_O1z2JdjmB-y2I-ImInI4-Ic7gdexIY6PuP8b0nmsdh-IeMC6sWyyC-BmOh8bHtBEUSQfVqddNG2ESmolVLbSJK3K2jumul6d_cNHMtbJXTYakK9_PzKb9Epl-mdWssfFK2Htg |
link.rule.ids | 230,309,786,891,25594,76903 |
linkProvider | European Patent Office |
linkToHtml | http://utb.summon.serialssolutions.com/2.0.0/link/0/eLvHCXMwfZ3fT4MwEMcvy_wx33Rq_DG1iYY34hbKGA-L2QpzKB0LLWZ7WoBhYmLY4jD--x51U5_2RNILDTS53n3g7luAO4TkzKStWLfmVlOnlpnqnTg1dDOmrY5lZBjSy-ZkPmoPI_o0MScVeN_0wiid0C8ljogelaK_F2q_Xv59xHJUbeXqPnnDocXDQHYdbU3HSDOYUmtOv-uOAydgGmPdSGijUNmQXTB96SEr7VgIhQqWXvplX8ryf1AZHMLuGOfLiyOoZHkdamxz9lod9vn6l3cd9lSNZrrCwbUfro4hcDwhQ68f4b5DVOU8XjEx5d6Puq0gCHeER770xr5LuMuDcEpK-dvHsFfew7yQRZ4kYiqky8UJ3A5cyYY6PuPsd0lmkfj_QsYpVPNFnp0BMTH42PacIogg-zTbybxlI1JQK6G2Ecev59DYNtPFdvMN1IaS-zPfGz1fwkFpUqKHzQZUi4_P7AoDdJFcq3X9BpKniqA |
openUrl | ctx_ver=Z39.88-2004&ctx_enc=info%3Aofi%2Fenc%3AUTF-8&rfr_id=info%3Asid%2Fsummon.serialssolutions.com&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Apatent&rft.title=DISTRIBUTED+GROUPED+TERMINATIONS+FOR+MULTIPLE+MEMORY+INTEGRATED+CIRCUIT+SYSTEMS&rft.inventor=Contreras%2C+John+Thomas&rft.inventor=Mobin%2C+Sayed&rft.inventor=Rajendra%2C+Srinivas&rft.inventor=Zakai%2C+Rehan+Ahmed&rft.date=2021-12-30&rft.externalDBID=A1&rft.externalDocID=US2021407565A1 |